公开(公告)号：US07949482B2

公开(公告)日：2011-05-24

申请号：US12142294

申请日：2008-06-19

申请人： Fadi H. Gebara ,  Jerry D. Hayes ,  John P. Keane ,  Sani R. Nassif ,  Jeremy D. Schaub

发明人： Fadi H. Gebara ,  Jerry D. Hayes ,  John P. Keane ,  Sani R. Nassif ,  Jeremy D. Schaub

IPC分类号： G01L1/00

CPC分类号： G01R31/31725 ,  G01R31/2856

摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

摘要翻译： 一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。 可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。 为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量 由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。 延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

公开(公告)号：US20110078641A1

公开(公告)日：2011-03-31

申请号：US12569421

申请日：2009-09-29

申请人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

发明人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

摘要翻译： 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US07870525B2

公开(公告)日：2011-01-11

申请号：US12122451

申请日：2008-05-16

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

公开(公告)号：US20100327892A1

公开(公告)日：2010-12-30

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/02

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US07834649B2

公开(公告)日：2010-11-16

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07818137B2

公开(公告)日：2010-10-19

申请号：US12361891

申请日：2009-01-29

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Sani R. Nassif

IPC分类号： G01R27/00 ,  G01R31/00 ,  G01R31/14

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/318533 ,  G01R31/318558

摘要： A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.

摘要翻译： 用于快速确定器件电容变化统计的测试电路提供了一种使用低计算能力和易于获得的测试设备来确定过程变化和参数统计的机制。 在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。 阵列的测试输出提供依赖于特定器件参数的电流或电压。 器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。 测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

公开(公告)号：US20100225348A1

公开(公告)日：2010-09-09

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07782076B2

公开(公告)日：2010-08-24

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

公开(公告)号：US07768814B2

公开(公告)日：2010-08-03

申请号：US12233856

申请日：2008-09-19

申请人： Kanak B. Argawal ,  Jerry D. Hayes

发明人： Kanak B. Argawal ,  Jerry D. Hayes

IPC分类号： G11C11/24

CPC分类号： G11C29/50 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

摘要： The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (Ccell) of the storage cell; measuring a local bitline capacitance (Cbl) of the storage cell; measuring a transfer device voltage (VT) of the storage cell; computing a transfer ratio (TR) for the storage cell; and measuring a data retention time for the storage cell.

摘要翻译： 本发明提供了一种用于测量用于提高DRAM的产量和性能的动态随机存取存储器（DRAM）处理参数的统计量的方法。 测量电容的基本原理类似于基于电荷的电容（CBCM），但是本发明在若干基本方面是不同的。 在一个实施例中，该方法包括接收DRAM的存储单元的选择; 测量存储单元的存储单元电容（Ccell）; 测量存储单元的局部位线电容（Cbl）; 测量存储单元的传送装置电压（VT）; 计算存储单元的传输比（TR）; 并测量存储单元的数据保留时间。

公开(公告)号：US07716616B2

公开(公告)日：2010-05-11

申请号：US11930924

申请日：2007-10-31

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。