公开(公告)号：US20070287239A1

公开(公告)日：2007-12-13

申请号：US11451264

申请日：2006-06-12

申请人： Jong Shik Yoon ,  Amitava Chatterjee ,  Kayvan Sadra ,  Shaopin Tang

发明人： Jong Shik Yoon ,  Amitava Chatterjee ,  Kayvan Sadra ,  Shaopin Tang

IPC分类号： H01L21/338 ,  H01L21/425

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

摘要翻译： 公开了用于形成具有对称注入的有源区并且减少交叉扩散的SRAM单元的方法。 一种方法包括图案化覆盖在半导体衬底上的抗蚀剂层，以形成对称地位于电池的有源区的相对侧上的抗蚀剂结构，使用第一注入使用抗蚀剂结构作为注入掩模注入一种或多种掺杂剂物质， 衬底相对于第一注入约180度，以及使用抗蚀剂结构作为植入掩模将一种或多种掺杂剂物质注入到半导体衬底中，其中第二注入。 还公开了执行对称角度注入的方法，以在电池内提供减小的交叉扩散，包括在电池的有源区域的相对侧上图案化等间隔的抗蚀剂结构，以同样地遮蔽横向相对的第一和第二倾斜植入物。

公开(公告)号：US07018888B2

公开(公告)日：2006-03-28

申请号：US10902902

申请日：2004-07-30

申请人： Brian E. Goodlin ,  Amitava Chatterjee ,  Shirin Siddiqui ,  Jong S. Yoon

发明人： Brian E. Goodlin ,  Amitava Chatterjee ,  Shirin Siddiqui ,  Jong S. Yoon

IPC分类号： H01L21/8238

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).

摘要翻译： 本发明提供一种制造半导体器件的方法和用于制造包括该半导体器件的集成电路的方法。 除了其他步骤之外，制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有侧壁间隔物（210或410） 源极/漏极注入（310,510）到靠近栅极结构（130）的衬底（110）中。 所述方法还包括：移除所述侧壁间隔物（210或410）的至少一部分并且在去除所述侧壁间隔物的所述至少一部分之后对所述源/漏植入物（310,510）进行退火以形成源极/漏极区域（710） （210或410）。

公开(公告)号：US06791383B2

公开(公告)日：2004-09-14

申请号：US10265850

申请日：2002-10-07

申请人： Amitava Chatterjee

发明人： Amitava Chatterjee

IPC分类号： H03L706

CPC分类号： H01L23/5222 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention describes a method for reducing the leakage current in thin gate dielectric MOS capacitors in integrated circuits. A bias voltage is determined for the MOS capacitor such that the capacitor area and leakage current constraints are satisfied. The MOS capacitor is not biased in inversion.

摘要翻译： 本发明描述了一种用于减小集成电路中的薄栅介质MOS电容器中的漏电流的方法。 确定MOS电容器的偏置电压，使得满足电容器面积和漏电流限制。 MOS电容器在反相中没有偏置。

公开(公告)号：US06767810B2

公开(公告)日：2004-07-27

申请号：US10629514

申请日：2003-07-29

申请人： Craig T. Salling ,  Amitava Chatterjee ,  Youngmin Kim

发明人： Craig T. Salling ,  Amitava Chatterjee ,  Youngmin Kim

IPC分类号： H01L218249

CPC分类号： H01L27/0277

摘要： An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad. In the first embodiment, the space includes a dummy gate; in the second embodiment, an isolation region; in the third embodiment, the space a protected, stable surface.

摘要翻译： 位于半导体芯片表面的隔离沟槽之间的集成电路，包括具有第一电阻率的第一导电类型的第一阱。 该第一阱具有比第一电阻率更高的电阻率的浅埋入区，在隔离沟槽之间延伸并由补偿掺杂工艺产生。 电路还包括延伸到隔离沟槽之间的表面的相反导电类型的第二阱，具有接触区域并与第一阱的浅埋入区域基本上平行于表面形成结。 最后，电路具有位于第二阱中的MOS晶体管，与接触区域间隔开，并且在表面具有源极，栅极和漏极区域。 该空间是预定的，以在I / O晶体管中产生一个小的电压降，用于调节信号和对焊盘的功率，或者ESD电路中的大的电压降，用于保护连接到焊盘的有源电路。 在第一实施例中，空间包括虚拟门; 在第二实施例中，隔离区域; 在第三实施例中，空间是受保护的，稳定的表面。

公开(公告)号：US06682980B2

公开(公告)日：2004-01-27

申请号：US10139672

申请日：2002-05-06

申请人： P. R. Chidambaram ,  Amitava Chatterjee ,  Srinivasan Chakravarthi

发明人： P. R. Chidambaram ,  Amitava Chatterjee ,  Srinivasan Chakravarthi

IPC分类号： H01L21336

CPC分类号： H01L29/6656 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586

摘要： The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the semiconductor substrate with a channel region therebetween. The source and drain region of the semiconductor substrate are then subjected to an angled amorphization implant, wherein the angled amorphization implant amorphizes the semiconductor substrate thereat and in portions of the channel region near a lateral edge of the gate, thereby defining an amorphized source extension region and drain extension region, respectively. The method continue with an implantation of the source region and the drain region with a lightly doped p-type source/drain implant, followed by an anneal to repair damage in the semiconductor substrate due to the pre-amorphizing implant and the lightly doped source/drain implantation. The amorphized source and drain extension regions advantageously reduce a lateral diffusion thereof during the anneal.

摘要翻译： 本发明涉及一种在半导体衬底内形成PMOS晶体管的方法，包括在半导体衬底的n型部分上形成栅极，由此在沟道中限定半导体衬底中的源极区和漏极区 区域。 然后对半导体衬底的源极和漏极区域进行成角度的非晶化注入，其中成角度的非晶化植入物使半导体衬底在其上方和在栅极的侧边缘附近的沟道区域的部分中非晶化，从而限定非晶化源极延伸区域 和漏极延伸区域。 该方法继续用轻掺杂的p型源极/漏极注入来注入源极区域和漏极区域，随后进行退火以修复半导体衬底中的损伤，这是由于预非晶化注入和轻掺杂源极/ 漏极植入。 非晶化源极和漏极延伸区域有利地在退火期间减小其横向扩散。

公开(公告)号：US06598214B2

公开(公告)日：2003-07-22

申请号：US10001343

申请日：2001-10-25

申请人： Amitava Chatterjee ,  Sreedhar Natarajan

发明人： Amitava Chatterjee ,  Sreedhar Natarajan

IPC分类号： G06F1750

CPC分类号： G06F17/5063

摘要： A method (40) of designing a circuit comprising a plurality of transistors (10, 46T, 60T). Each transistor of the plurality of transistors comprises an active region, a gate (G1, G2), a first source/drain (S/D1, S/D3) in the active region, a second source/drain in the active region, and at least one contact in each of the first source/drain and the second source/drain. The method comprises various steps. The method specifies a first set of distances for each transistor in a first set (10) of transistors in the plurality of transistors, wherein the first set of distances comprises a gate length (Lg), a gate width (Wg), and a distance representative of one or both of a first contact-to-edge distance (CTE1) and a first contact-to-gate distance (CTG1). The method also specifies (46) a second set of distances for each transistor in a second set (46T, 60T) of transistors in the plurality of transistors, wherein the second set of distances comprises a gate length (Lg), a gate width (Wg), and a distance representative of one or both of a second contact-to-edge distance (CTE2) and a second contact-to-gate distance (CTG2). For the method specifications, either or both the second contact-to-edge distance is greater than the first contact-to-edge distance and the second contact-to-gate distance is greater than the first contact-to-gate distance. Also for the method specifications, for each transistor in the second set of transistors, the step of specifying a second set of distances is responsive to a determination (44, 48) of a benefit from a larger drive current to be provided by the transistor in the second set of transistors.

公开(公告)号：US06514810B1

公开(公告)日：2003-02-04

申请号：US09920157

申请日：2001-08-01

申请人： Youngmin Kim ,  Amitava Chatterjee

发明人： Youngmin Kim ,  Amitava Chatterjee

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/823807

摘要： A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

摘要翻译： 用于模拟应用的掩埋沟道PMOS晶体管被集成到数字CMOS工艺中。 通过在半导体衬底中注入所有n型和p型衬底以形成用于数字CMOS工艺的n阱和p阱区域的区域来形成第三阱区（105）。 栅电介质层（50）和栅极层（109）形成在第三阱（105）的上方并且包括掩埋沟道PMOS晶体管的栅叠层。 用于形成漏极延伸区域和CMOS晶体管的源极和漏极区域的注入用于完成掩埋沟道PMOS晶体管。

公开(公告)号：US06479339B2

公开(公告)日：2002-11-12

申请号：US09967207

申请日：2001-09-28

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/266 ,  H01L21/823814

摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the formation of the LDD regions 180, 220, and the pocket regions 190, 230 of the core transistors 152, 154. The LDD regions 240, 200 of the I/O or analog transistors 156, 158 are simultaneously formed during the process.

公开(公告)号：US06180978B2

公开(公告)日：2001-01-30

申请号：US09216216

申请日：1998-12-18

申请人： Amitava Chatterjee ,  Richard A. Chapman ,  Syed Suhail Murtaza

发明人： Amitava Chatterjee ,  Richard A. Chapman ,  Syed Suhail Murtaza

IPC分类号： H01L2994

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/78

摘要： A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.

摘要翻译： 在CMOS晶体管中使用反掺杂外延硅（与衬底类型相反掺杂）在保持突然的沟道分布的同时形成掩埋层。 可以使用升高（或提升）的源极/漏极设计形成具有突然的源极/漏极分布的浅源极/漏极结。 本发明包括一种晶体管结构，其包括掺杂硅衬底和形成在衬底上的相对掺杂的外延硅层。 栅极形成在外延层上，栅极在栅极下方的外延层中限定沟道区。 在栅极的相对侧上的外延硅层上形成层，并且与栅极电隔离。

公开(公告)号：US6117741A

公开(公告)日：2000-09-12

申请号：US226237

申请日：1999-01-05

申请人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

发明人： Amitava Chatterjee ,  Wei William Lee ,  Greg A. Hames ,  Quzhi He ,  Iqbal Ali ,  Maureen A. Hanratty

IPC分类号： H01L21/311 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/31111 ,  H01L29/66545

摘要： A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

摘要翻译： 提供一种具有改进的侧壁栅极结构和结构方法的晶体管。 改进的侧壁栅极结构可以包括具有沟道区域（20）的半导体衬底（12）。 栅极绝缘体（36）可以邻近半导体衬底（12）的沟道区域（20）。 栅极（38）可以邻近栅极绝缘体（36）形成。 侧壁绝缘体（28）可以邻近门（38）的一部分形成。 侧壁绝缘体（28）由氮氧化硅材料构成。 外延层（30）可以邻近侧壁绝缘体（28）的一部分并且基本上在沟道区域（20）的外侧邻近半导体衬底（12）形成。 缓冲层（32）可以邻近侧壁绝缘体（28）的一部分并且邻近外延层（30）形成。