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    Micro-Electro-Mechanical System Tiltable Lens
    41.
    发明申请
    Micro-Electro-Mechanical System Tiltable Lens 有权
    微机电系统倾斜透镜

    公开(公告)号：US20110134504A1

    公开(公告)日：2011-06-09

    申请号：US12632040

    申请日：2009-12-07

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G02B26/08 ,  G06F17/50 ,  H01L21/30

    CPC分类号： G02B26/08 ,  B81B3/004 ,  B81B2201/047 ,  G02B7/023 ,  G02B26/0875

    摘要： A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided.

    摘要翻译： 可倾斜微电机械（MEMS）系统透镜包括位于绝缘体上半导体（SOI）衬底的前表面上的微观透镜和围绕微观透镜周边的半导体边缘。 位于不同高度的两个水平半导体光束设置在顶部半导体层内。 可以通过在透镜边缘和两个半导体束中的一个之间施加电偏压来倾斜微观透镜，从而改变光束通过微透镜的路径。 可以使用可倾斜微镜透镜的阵列来形成具有可变焦距的复合透镜。 还提供了这种可倾斜MEMS透镜的设计结构。

    Spacer Linewidth Control
    43.
    发明申请
    Spacer Linewidth Control 有权
    间隔线宽控制

    公开(公告)号：US20100261351A1

    公开(公告)日：2010-10-14

    申请号：US12622557

    申请日：2009-11-20

    申请人： James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Paterson ,  Jed H. Rankin

    发明人： James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Paterson ,  Jed H. Rankin

    IPC分类号： H01L21/302 ,  H01L21/306

    CPC分类号： H01L21/31144

    摘要： A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

    摘要翻译： 用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。 保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。 用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻 的部分蚀刻的间隔材料层。 用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

    Back-End-of-Line Resistive Semiconductor Structures
    47.
    发明申请
    Back-End-of-Line Resistive Semiconductor Structures 有权
    后端电阻半导体结构

    公开(公告)号：US20100038754A1

    公开(公告)日：2010-02-18

    申请号：US12191683

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

    METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY
    48.
    发明申请
    METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY 失效
    在非易失性随机存取存储器中用作存储器单元的器件结构的制作方法

    公开(公告)号：US20090280607A1

    公开(公告)日：2009-11-12

    申请号：US12117950

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7881 ,  H01L27/1203 ,  H01L29/66825

    摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

    摘要翻译： 制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。 该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，以及部分地移除第二半导体本体以限定邻近 第一半导体体的通道。 该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极， 与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

    DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY
    49.
    发明申请
    DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY 失效
    非易失性随机访问存储器的存储单元的设备结构和非易失性随机存取存储器的设计结构

    公开(公告)号：US20090278185A1

    公开(公告)日：2009-11-12

    申请号：US12118241

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00 ,  G06F9/455

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42324

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.

    摘要翻译： 非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。 器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。 半导体本体包括源极，漏极以及源极和漏极之间的沟道。 浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。 第一电介质层设置在半导体本体的沟道和浮栅之间。 第二介电层设置在控制栅电极和浮栅电极之间。