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    Four-stroke engine with an oil spray generating assembly for lubrication
    42.
    发明授权
    Four-stroke engine with an oil spray generating assembly for lubrication 失效
    具有用于润滑的喷油发电组件的四冲程发动机

    公开(公告)号：US06769391B1

    公开(公告)日：2004-08-03

    申请号：US10411230

    申请日：2003-04-11

    Applicant: Andy Lee ,  Shaw-Liung Teng

    Inventor： Andy Lee ,  Shaw-Liung Teng

    IPC: F01M106

    CPC classification number: F02B63/02 ,  F01M1/04 ,  F01M1/08 ,  F01M9/10 ,  F01M11/064 ,  F02B2075/027 ,  F16N7/32

    Abstract: A four-stroke internal combustion engine includes a crankcase with a bottom, an oil pan and an oil spray generating assembly. The oil spray generating assembly having a closed sidewall, a valve, a bottom cap and nozzles is attached to the bottom of the crankcase and is enclosed by the oil pan. The closed sidewall is formed at the bottom of the crankcase to define a mist chamber enclosed by the bottom cap. The valve is mounted in the mist chamber with a valve port defined through the crankcase and a resilient valve flap corresponding to the valve port attached to the bottom of the crankcase. The nozzles are respectively mounted in the bottom cap out of the mist chamber inside the closed sidewall. The operation of the engine will produce an oil vapor for lubrication with the lubricating oil flowing out of the nozzles.

    Abstract translation: 四冲程内燃机包括具有底部的曲轴箱，油盘和喷油发生组件。 具有闭合侧壁，阀，底盖和喷嘴的喷油发生组件附接到曲轴箱的底部并被油盘包围。 封闭的侧壁形成在曲轴箱的底部，以限定由底盖包围的雾室。 阀安装在雾室中，阀口通过曲轴箱限定，弹性阀瓣对应于连接到曲轴箱底部的阀口。 喷嘴分别安装在封闭侧壁内的雾室中的底盖中。 发动机的操作将产生用于润滑的油蒸汽，其中润滑油从喷嘴流出。

    Fracturable lookup table and logic element
    47.
    发明授权
    Fracturable lookup table and logic element 有权
    可破坏的查找表和逻辑元素

    公开(公告)号：US07800401B1

    公开(公告)日：2010-09-21

    申请号：US11841727

    申请日：2007-08-20

    Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    IPC: H03K19/177

    CPC classification number: H03K19/177

    Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

    Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

    Distributed memory in field-programmable gate array integrated circuit devices
    48.
    发明授权
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US07656191B2

    公开(公告)日：2010-02-02

    申请号：US12156403

    申请日：2008-05-30

    Applicant: David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    Inventor： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC: H03K19/177

    CPC classification number: G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    Abstract translation: 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

    Unified communications systems and methods
    49.
    发明申请
    Unified communications systems and methods 审中-公开
    统一的通信系统和方法

    公开(公告)号：US20090177735A1

    公开(公告)日：2009-07-09

    申请号：US12317714

    申请日：2008-12-22

    Applicant: Glenn Algie ,  Haseeb Akhtar ,  Andy Lee

    Inventor： Glenn Algie ,  Haseeb Akhtar ,  Andy Lee

    IPC: G06F15/16 ,  H04L9/00 ,  G06Q30/00 ,  H04L9/32 ,  H03M7/00 ,  G06F3/01

    CPC classification number: H04L65/4084 ,  G06Q30/0601 ,  G06Q30/0603 ,  H04L63/105 ,  H04L67/14 ,  H04L67/303 ,  H04L69/08

    Abstract: Systems and methods for providing digital content are disclosed through a universal medial connection API, which include registering an application to be used during a session, loading policies to be used during the session, and identifying hardware features to be used during the session. These systems and methods also include steering data to be used during a session and presenting data to an endpoint during the session. The content is delivered from a first client to a second client according to the policies and hardware features that are available during the session.

    Abstract translation: 用于提供数字内容的系统和方法通过通用中间连接API公开，该通用中间连接API包括在会话期间注册要使用的应用，加载在会话期间使用的策略以及识别在会话期间要使用的硬件特征。 这些系统和方法还包括在会话期间使用的导向数据，并且在会话期间向端点呈现数据。 内容根据会话期间可用的策略和硬件功能从第一个客户端传送到第二个客户端。

    Distributed memory in field-programmable gate array integrated circuit devices
    50.
    发明申请
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US20080231316A1

    公开(公告)日：2008-09-25

    申请号：US12156403

    申请日：2008-05-30

    Applicant: David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    Inventor： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC: H03K19/177

    CPC classification number: G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    Abstract translation: 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

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