公开(公告)号：US07395372B2

公开(公告)日：2008-07-01

申请号：US10714105

申请日：2003-11-14

申请人： Anthony Correale, Jr. ,  James N. Dieffenderfer ,  Robert L. Goldiez ,  Thomas P. Speier ,  William R. Reohr

发明人： Anthony Correale, Jr. ,  James N. Dieffenderfer ,  Robert L. Goldiez ,  Thomas P. Speier ,  William R. Reohr

IPC分类号： G06F13/00 ,  G06F1/32

CPC分类号： G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

摘要： A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data stored in each of the ways. A translation device determines from a system address a tag identifying one of the ways. A first comparator compares tags in the address with a tag stored in the first tag memory. A second comparator compares a tag in the address with a tag stored in the second tag memory. A clock signal supplies clock signals to one or both of the ways in response to an access mode signal. The system can be operated so that either both ways of the associative data cache are clocked, in a high speed access mode, or it can apply clock signals to only one of the ways selected by an output from the first and second comparators in a power efficient mode of operation.

摘要翻译： 一种用于访问具有至少两种在相同地址处存储数据的方式的数据高速缓存的系统和方法。 第一和第二标签存储器存储识别以每种方式存储的数据的第一和第二组标签。 翻译装置从系统地址确定识别方式之一的标签。 第一个比较器将地址中的标签与存储在第一标签存储器中的标签进行比较。 第二比较器将地址中的标签与存储在第二标签存储器中的标签进行比较。 响应于访问模式信号，时钟信号将时钟信号提供给一种或两种方式。 可以对系统进行操作，使得关联数据高速缓存的两种方式都以高速访问模式被计时，或者它可以将时钟信号仅以来自第一和第二比较器的输出的功率中的一种方式应用于时钟信号 高效的运行模式。

公开(公告)号：US07340712B2

公开(公告)日：2008-03-04

申请号：US11142566

申请日：2005-06-01

申请人： Anthony Correale, Jr.

发明人： Anthony Correale, Jr.

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The present invention provides a system and method for providing a standard cell library for reduced leakage and improved performance. The standard cell library comprises at least two sets of threshold voltage cells. At least one of the sets includes non-mixed threshold voltage cells. At least one of the sets includes mixed threshold voltage cells. The mixed threshold voltage cells have at least one threshold voltage cell having a first threshold voltage and a second threshold voltage cell having a second threshold voltage. The first and second threshold voltages are different. The mixed threshold voltage cells have substantially the same footprint as the non-mixed threshold voltage cell.

摘要翻译： 本发明提供了一种用于提供用于减少泄漏和改进性能的标准单元库的系统和方法。 标准单元库包括至少两组阈值电压单元。 这些组中的至​​少一个包括非混合阈值电压单元。 这些组中的至​​少一个包括混合阈值电压单元。 混合阈值电压单元具有至少一个具有第一阈值电压的阈值电压单元和具有第二阈值电压的第二阈值电压单元。 第一和第二阈值电压是不同的。 混合阈值电压单元具有与非混合阈值电压单元基本相同的占空比。

公开(公告)号：US07224063B2

公开(公告)日：2007-05-29

申请号：US09871883

申请日：2001-06-01

申请人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

发明人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC分类号： H01L23/52

CPC分类号： H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

摘要翻译： 一种互连结构，包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下层导线的侧面和底部上的下导电衬垫; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

公开(公告)号：US07119578B2

公开(公告)日：2006-10-10

申请号：US10720466

申请日：2003-11-24

申请人： Anthony Correale, Jr. ,  Rajiv V. Joshi ,  David S. Kung ,  Zhigang Pan ,  Ruchir Puri

发明人： Anthony Correale, Jr. ,  Rajiv V. Joshi ,  David S. Kung ,  Zhigang Pan ,  Ruchir Puri

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

公开(公告)号：US07091574B2

公开(公告)日：2006-08-15

申请号：US10387728

申请日：2003-03-13

申请人： Anthony Correale, Jr.

发明人： Anthony Correale, Jr.

IPC分类号： H01L29/00

CPC分类号： G06F17/5072 ,  H01L23/5286 ,  H01L27/118 ,  H01L2924/0002 ,  H01L2924/00

摘要： A voltage island is disclosed. The voltage island comprises a physical domain and a lower voltage supply rail within the physical domain. The voltage island also includes an upper voltage supply rail within the physical domain. The physical domain is coupled to the appropriate voltage supply rail to ensure reverse biased junctions. Accordingly, a system in accordance with the present invention allows circuit placements associated with multiple voltage islands within a common circuit row or even adjacent circuit rows to be utilized in which the area effectiveness is greatly improved. The use of common Nwell biasing connected to the higher power supply ensures no forward biased junctions and allows butted circuit placement in cases where the other circuit physical constraints permit. This configuration will minimize the density loss associated multiple voltage island implementations.

摘要翻译： 公开了电压岛。 电压岛包括物理域内的物理域和较低电压电源轨。 电压岛还包括物理域内的上电压供电轨。 物理域耦合到适当的电源电源轨，以确保反向偏置的结。 因此，根据本发明的系统允许利用公共电路行或甚至相邻电路行中的多个电压岛的电路布置，其中区域有效性被大大提高。 使用连接到较高电源的公共Nwell偏置可确保没有正向偏置的结，并允许在其他电路物理限制允许的情况下对接电路放置。 该配置将使与多个电压岛实现相关的密度损失最小化。

公开(公告)号：US06762638B2

公开(公告)日：2004-07-13

申请号：US10065228

申请日：2002-10-16

申请人： Anthony Correale, Jr. ,  William James Goodall, III

发明人： Anthony Correale, Jr. ,  William James Goodall, III

IPC分类号： H03K3289

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356008

摘要： A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

摘要翻译： 公开了一种在待机模式下功耗降低的方法和触发器。 在第一方面，触发器包括适于耦合到第一电源的第一锁存器和耦合到第一锁存器并适于耦合到第二电源的第二锁存器。 第一和第二电源是可独立控制的，以便在待机模式下最小化功耗。 在第二方面，还公开了一种用于最小化触发器的功耗的方法。 触发器包括第一锁存器和与其耦合的第二锁存器。 该方法包括提供耦合到主锁存器的第一独立可控电源; 以及提供耦合到从锁存器的第二独立可控电源。 该方法还包括响应于省电模式的检测而降低第一和第二电源中的至少一个的电压。

公开(公告)号：US06657912B1

公开(公告)日：2003-12-02

申请号：US10393286

申请日：2003-03-20

申请人： Anthony Correale, Jr. ,  Nishith Rohatgi

发明人： Anthony Correale, Jr. ,  Nishith Rohatgi

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C2207/007 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory bit line multiplexor circuit is disclosed. The circuit comprises at least one memory cell arrangement. The circuit includes a first active device coupled to the at least one memory cell arrangement and for coupling a first node to a second node within the circuit. The first active device is controlled by a write through read (!wtr) signal. The circuit includes a second active device coupled to the second node and a gate. The gate has a first input coupled to the first node; a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit. The gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit. A circuit in accordance with the present invention is disclosed in which the most power, and area efficient realizations can be employed for applications requiring broad power supply operating ranges. The circuit employs a simple logic gate system configured to create a self-timed pulsed stimulus for allowing improved performance over a very broad Vdd operation range while simultaneously reducing power.

摘要翻译： 公开了一种存储器位线多路复用器电路。 该电路包括至少一个存储单元布置。 该电路包括耦合到该至少一个存储单元布置并用于将第一节点耦合到该电路内的第二节点的第一有源器件。 第一个有源器件由写入（！wtr）信号控制。 电路包括耦合到第二节点和门的第二有源装置。 门具有耦合到第一节点的第一输入; 耦合到！WTR信号的第二输入，以及由电路的输出的反相控制的第三输入。 门和第二有源器件提供脉冲自定时响应，在优化电路性能的同时最大限度地降低功耗。 公开了根据本发明的电路，其中最大功率和面积有效的实现可以用于需要宽电源工作范围的应用。 该电路采用简单的逻辑门系统，配置为创建自定时脉冲激励，以便在非常宽的Vdd运行范围内提高性能，同时降低功耗。

公开(公告)号：US06570401B2

公开(公告)日：2003-05-27

申请号：US09758054

申请日：2001-01-10

申请人： Anthony Correale, Jr. ,  Terry Cain Coughlin, Jr. ,  Douglas Willard Stout

发明人： Anthony Correale, Jr. ,  Terry Cain Coughlin, Jr. ,  Douglas Willard Stout

IPC分类号： H03K19007

CPC分类号： H03K19/00315

摘要： The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

公开(公告)号：US06441600B1

公开(公告)日：2002-08-27

申请号：US09766200

申请日：2001-01-19

申请人： Francois Ibrahim Atallah ,  Anthony Correale, Jr.

发明人： Francois Ibrahim Atallah ,  Anthony Correale, Jr.

IPC分类号： G01R1900

CPC分类号： G01R31/2882

摘要： A system and method for accurately measuring the duty cycle of an input periodic pulsed signal. The system includes a device for converting the input signal to be measured into a first dc voltage and, a device maintaining representations of potential duty cycle values that are selectable in an iterative fashion. At each iteration, in response to a selected duty cycle value, a second dc voltage is generated that represents the difference between the duty cycle of the input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value. A selection mechanism responds to the first and second dc voltages for selecting a different encoded duty cycle for a successive iteration. The system selects an encoded duty cycle value at each iteration until the first and second dc voltages match. At such time, the current selected encoded duty cycle value represents the duty cycle of the input voltage for output thereof. By representing the input signal's duty cycle as a dc voltage, the system may measure the input signal's duty cycle accurately regardless of its frequency.

摘要翻译： 一种用于精确测量输入周期性脉冲信号占空比的系统和方法。 该系统包括用于将待测量的输入信号转换为第一直流电压的装置，以及维持以迭代方式选择的潜在占空比值的表示的装置。 在每次迭代中，响应于所选择的占空比值，产生表示要测量的输入信号的占空比与由当前选择的编码占空比值表示的占空比之间的差的第二直流电压。 选择机构响应第一和第二直流电压以选择用于连续迭代的不同的编码占空比。 系统在每次迭代时选择编码的占空比值，直到第一和第二直流电压相匹配。 此时，当前选择的编码占空比值表示用于其输出的输入电压的占空比。 通过将输入信号的占空比表示为直流电压，系统可以准确地测量输入信号的占空比，而不管其频率如何。

公开(公告)号：US06335637B1

公开(公告)日：2002-01-01

申请号：US09541196

申请日：2000-04-03

申请人： Anthony Correale, Jr. ,  Terry C. Coughlin, Jr. ,  David W. Stout

发明人： Anthony Correale, Jr. ,  Terry C. Coughlin, Jr. ,  David W. Stout

IPC分类号： H03K190175

CPC分类号： H03K19/00315 ,  H03K19/09429

摘要： The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

摘要翻译： 本发明的保护电路解决了由两电源CMOS集成电路中的一个电源的损耗引起的不确定的逻辑电平的问题。 本发明的电路取代了电源排序的典型方案来解决问题。 本文所公开的电路检测核心电压的状态，并且当核心电压被检测为关闭时，禁用输出驱动器。 禁用的驱动器处于高阻抗状态，从而消除了损坏的可能性，并消除了对电源排序的需要。 本发明还可以防止在正常工作期间集成电路核心电压VDD，电源的突然损失。