公开(公告)号：US10707162B2

公开(公告)日：2020-07-07

申请号：US16599011

申请日：2019-10-10

Applicant: Apple Inc.

Inventor： Yi Chun A. Fu ,  Mansour Keramat ,  Vijay Srinivas

IPC: H01L23/522 ,  H01G4/01 ,  H01G4/228 ,  H01L49/02 ,  H01G4/38 ,  H03M1/20 ,  H03M1/46 ,  H01G4/06 ,  H03M1/80

Abstract: Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

公开(公告)号：US20200153448A1

公开(公告)日：2020-05-14

申请号：US16745173

申请日：2020-01-16

Applicant: Apple Inc.

Inventor： Tao Wang ,  Mansour Keramat ,  Yi Chun A. Fu

IPC: H03M1/10 ,  H01L27/10 ,  H01L23/528

Abstract: Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.

公开(公告)号：US20190373198A1

公开(公告)日：2019-12-05

申请号：US16272283

申请日：2019-02-11

Applicant: Apple Inc.

Inventor： Nick Chang ,  Mansour Keramat ,  Hyunsik Park ,  Brian Liebowitz ,  Ashirwad Bahukhandi

IPC: H04N5/374 ,  H04N5/378 ,  H04N5/3745 ,  H04N5/365 ,  H04N5/367 ,  H04N5/376 ,  H01L27/146

Abstract: A pixel circuit and method for operating the same is disclosed. The circuit includes a first driver circuit coupled to receive an analog pixel data, transfer signal and reset signal. The circuit further includes a source follower transistor having a source terminal coupled to a column node, and a gate terminal coupled to the first driver circuit. The circuit further includes a second driver circuit coupled to receive the transfer signal and the reset signal. The second driver circuit is capacitively coupled to the column node through a first capacitor.

公开(公告)号：US09998134B1

公开(公告)日：2018-06-12

申请号：US15658020

申请日：2017-07-24

Applicant: Apple Inc.

Inventor： Dusan Stepanovic ,  Mansour Keramat

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1014 ,  H03M1/1009 ,  H03M1/1042 ,  H03M1/12

Abstract: In various embodiments, at least one analog-to-digital converter (ADC) channel circuit may be used to convert an analog input signal into an output digital signal. A comparator threshold adjustment circuit may pseudorandomly modify at least one comparator threshold. A postprocessing circuit may identify, based on outputs of the ADC channel circuits, an ADC coefficient and may modify an output digital signal based on the ADC coefficient. As a result, the ADC channel circuits may more accurately convert the analog input signal into an output digital signal, as compared to a system that uses ADC channel circuits but does not include a postprocessing circuit. Further, a similar result may be obtained, as compared to a system that uses a higher gain amplifier, a higher speed amplifier, or both, but does not modify the one or more outputs.

公开(公告)号：US09418788B2

公开(公告)日：2016-08-16

申请号：US14643478

申请日：2015-03-10

Applicant: Apple Inc.

Inventor： Vijay Srinivas ,  Mansour Keramat ,  Yuan-Ju Chao

IPC: H03M1/66 ,  H01G4/01 ,  H01G4/228 ,  H01G4/38 ,  H01G4/12 ,  H03M1/46

CPC classification number: H01G4/01 ,  H01G4/129 ,  H01G4/228 ,  H01G4/38 ,  H03M1/468

Abstract: A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.

Abstract translation: 公开了一种电容器件，包括形成在下金属层上并耦合到第一端子的第一导体。 第二导体形成在上金属层上，并且多根导线分成一组，每组包括来自相应金属层的一根导线。 每组的第一和第二导线耦合到第二端子。 与第一导线相邻的每个组的第三线耦合到第一导体。 与第二导线相邻的每组的第四线耦合到第二导体。 组的第一子集的第五线耦合到第二导体，并且组的第二子集的第五线耦合到第一导体。 每组的第五根线与第一线和第二线相邻。

公开(公告)号：US20150263754A1

公开(公告)日：2015-09-17

申请号：US14643478

申请日：2015-03-10

Applicant: Apple Inc.

Inventor： Vijay Srinivas ,  Mansour Keramat ,  Yuan-Ju Chao

IPC: H03M1/46 ,  H01G4/01 ,  H01G4/12 ,  H01G4/228

CPC classification number: H01G4/01 ,  H01G4/129 ,  H01G4/228 ,  H01G4/38 ,  H03M1/468

Abstract: A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.

Abstract translation: 公开了一种电容器件，包括形成在下金属层上并耦合到第一端子的第一导体。 第二导体形成在上金属层上，并且多根导线分成一组，每组包括来自相应金属层的一根导线。 每组的第一和第二导线耦合到第二端子。 与第一导线相邻的每个组的第三线耦合到第一导体。 与第二导线相邻的每组的第四线耦合到第二导体。 组的第一子集的第五条线耦合到第二导体，并且组的第二子集的第五条线耦合到第一导体。 每组的第五根线与第一线和第二线相邻。

公开(公告)号：US09130519B1

公开(公告)日：2015-09-08

申请号：US13826050

申请日：2013-03-14

Applicant: Apple Inc.

Inventor： Mansour Keramat ,  Ali Meaamar

IPC: H03F1/02 ,  H03F3/45

CPC classification number: H03F1/02 ,  G11C27/026 ,  H03M1/1245

Abstract: A method and apparatus for combined linear, low-noise buffer and sampler for ADC (analog to digital converter) have been disclosed. In one implementation components contributing to sampling errors are included in a feedback path.

Abstract translation: 已经公开了用于ADC（模数转换器）的组合线性，低噪声缓冲器和采样器的方法和装置。 在一个实现中，有助于采样错误的部件被包括在反馈路径中。