Abstract:
A display may have an active area surrounded by a border area. The display may be a liquid crystal display having a liquid crystal layer sandwiched between a color filter layer and a thin-film transistor layer. The liquid crystal layer may be retained within the display using a ring of sealant that is dispensed along the border area on the thin-film transistor layer. The thin-film transistor layer may include at least a substrate, a dielectric layer formed over the substrate, a first planarization layer formed on the dielectric layer, and a second planarization layer formed on the first planarization layer. A first continuous trench structure may be formed along the border of the display to help prevent moisture seepage. A second trench structure that is separate from the first trench structure may be formed along the border of the display to help provide proper sealant adhesion.
Abstract:
A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.
Abstract:
A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
Abstract:
Electronic devices, storage medium containing instructions, and methods pertain to cancelling noise that results from application of voltages on gates of transistors in a display. One or more compensation or dummy drivers are used to apply a compensation voltage that is an inversion of voltages applied on the gates of the transistors.
Abstract:
Methods and devices useful in discharging an aberrant charge on a touch sensitive display of an electronic device are provided. By way of example, a an electronic device includes a power management and control circuitry configured to receive a first voltage signal and a second voltage signal from a display subsystem of a display of the electronic device, receive a third voltage signal from a touch subsystem of the display, provide a power signal to the display subsystem to activate the display subsystem when the display is determined to be in a temporarily inactive state. Providing the power signal to the display subsystem comprises discharging an aberrant charge based on the third voltage signal.
Abstract:
A gate drive circuit may include a latch circuit, a first transmission gate, and a second transmission gate. The first transmission gate and the second transmission gate may both be directly coupled to the latch circuit and may be directly coupled to a first gate line and a second gate line, respectively. The latch circuit may receive an electrical signal from a third gate line adjacent to the second gate line, such that the electrical signal is configured to reset a state of the latch circuit.
Abstract:
An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
Abstract:
An electronic device display may have an array of display pixels that are controlled using a grid of data lines and gate lines. The display may include compact gate driver circuits that perform gate driver operations to drive corresponding gate lines. Each compact gate driver circuit may include a first driver stage and a second driver stage. The first driver stage may receive a start pulse signal and produce a control signal. The control signal may be stored by a capacitor to identify a control state of the gate driver circuit. The second driver stage may receive the control signal, a clock signal, and a corresponding inverted clock signal and drive the corresponding gate line based on the received signals. The second driver stage may include pass transistor circuitry that passes the clock signal to the corresponding gate line and may include short circuit protection circuitry.
Abstract:
A display may be provided with integral touch functionality. The display may include a common electrode layer having row electrodes arranged in rows and column electrodes interposed between the row electrodes of each row. The row electrodes may be electrically coupled by conductive paths. The row and column electrodes may be coupled to touch sensor circuitry that uses the row and column electrodes to detect touch events. Each electrode of the common electrode layer may cover a respective portion of an array of pixels. Each pixel of the display may have a respective aperture. The conductive paths that electrically couple row electrodes of the common electrode layer may cover or otherwise block some light from passing through pixels, resulting in reduced apertures. Dummy structures may be provided for other pixels that modify the apertures of the other pixels to match the reduced apertures associated with the conductive paths.
Abstract:
A touch screen having touch circuitry integrated into a display pixel stackup. The touch screen can include a transistor layer, an LED layer and a first layer. The first layer can operate as an LED cathode during a display phase and as touch circuitry during a touch sensing phase. The transistor layer can be at least partially utilized for transitioning between the display phase and the touch sensing phase. The touch screen can be fabricated to reduce or eliminate damage to the LED layer.