公开(公告)号：US20240070071A1

公开(公告)日：2024-02-29

申请号：US18259827

申请日：2021-11-25

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite

IPC: G06F12/0811 ,  G06F12/0837 ,  G06F12/0875

CPC classification number: G06F12/0811 ,  G06F12/0837 ,  G06F12/0875

Abstract: A context-information-dependent instruction causes a context-information-dependent operation to be performed based on specified context information indicative of a specified execution context. A context information translation cache 10 stores context information translation entries each specifying untranslated context information and translated context information. Lookup circuitry 14 performs a lookup of the context information translation cache based on the specified context information, to identify whether the context information translation cache includes a matching context information translation entry which is valid and which specifies untranslated context information corresponding to the specified context information. When the matching context information translation entry is identified, the context-information-dependent operation is performed based on the translated context information specified by the matching context information translation entry.

公开(公告)号：US11669467B2

公开(公告)日：2023-06-06

申请号：US15768909

申请日：2016-09-06

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Richard Roy Grisenthwaite

IPC: G06F12/14 ,  G06F9/30 ,  G06F21/60 ,  G06F21/79 ,  G06F12/08 ,  G06F9/54 ,  G06F12/084

CPC classification number: G06F12/1441 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/544 ,  G06F12/084 ,  G06F12/14 ,  G06F12/1408 ,  G06F12/1475 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/79 ,  G06F2212/1052

Abstract: Processing circuitry performs processing operations specified by program instructions, and a decoder decodes memory access instructions to generate control signals to control the processing circuitry to perform memory access operations. The memory access instructions have respective encodings specifying protected memory access instructions corresponding to protected memory access operations and less-protected memory access instructions corresponding to less-protected memory access operations. The less-protected memory access operations are associated with less restrictive memory access conditions than the protected memory access operations.

公开(公告)号：US11615032B2

公开(公告)日：2023-03-28

申请号：US16625102

申请日：2018-06-01

Applicant: ARM LIMITED

Inventor： Matthew James Horsnell ,  Grigorios Magklis ,  Richard Roy Grisenthwaite

IPC: G06F3/06 ,  G06F12/1027 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0873

Abstract: A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

公开(公告)号：US11579873B2

公开(公告)日：2023-02-14

申请号：US17255001

申请日：2019-05-09

Applicant: Arm Limited

Inventor： Matthew James Horsnell ,  Grigorios Magklis ,  Richard Roy Grisenthwaite ,  Nathan Yong Seng Chong

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

公开(公告)号：US11461243B2

公开(公告)日：2022-10-04

申请号：US16959280

申请日：2018-08-30

Applicant: Arm Limited

Inventor： Richard Roy Grisenthwaite

IPC: G06F12/00 ,  G06F12/126 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/128

Abstract: An apparatus (2) comprises processing circuitry (4) to perform speculative execution of instructions; a main cache storage region (30); a speculative cache storage region (32); and cache control circuitry (34) to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative. This can help protect against potential security attacks which exploit cache timing side-channels to gain information about allocations into the cache caused by speculative memory accesses.

公开(公告)号：US11379233B2

公开(公告)日：2022-07-05

申请号：US17269216

申请日：2019-10-17

Applicant: Arm Limited

Inventor： Matthew James Horsnell ,  Richard Roy Grisenthwaite

IPC: G06F9/30 ,  G06F9/46 ,  G06F9/38

Abstract: In an apparatus with transactional memory support circuitry, for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.

公开(公告)号：US10949292B1

公开(公告)日：2021-03-16

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Michael Andrew Campbell ,  Alexander Alfred Hornung ,  Alex James Waugh ,  Klas Magnus Bruce ,  Richard Roy Grisenthwaite

IPC: G06F11/20 ,  G11C29/08 ,  G06F11/10 ,  G11C29/18 ,  G06F11/30

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US10802729B2

公开(公告)日：2020-10-13

申请号：US15574549

申请日：2016-04-26

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose

IPC: G06F3/06 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/14

Abstract: A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.

公开(公告)号：US10795675B2

公开(公告)日：2020-10-06

申请号：US15761476

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.

公开(公告)号：US10768938B2

公开(公告)日：2020-09-08

申请号：US16085053

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite ,  Simon John Craske ,  François Christopher Jacques Botman ,  Bradley John Smith

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F9/34

Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.