公开(公告)号：US11959950B2

公开(公告)日：2024-04-16

申请号：US17218670

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Zhiyao Xie ,  Shidhartha Das ,  Matthew James Walker ,  Kumara Guru Palaniswamy ,  Matthew Paul Elwood

IPC: G01R21/133 ,  G01R31/317 ,  G05B13/02 ,  G05B15/02 ,  G05F1/66 ,  G06F30/3308 ,  G06F30/367 ,  G06F119/06

CPC classification number: G01R21/133 ,  G01R31/31727 ,  G05B13/02 ,  G05B15/02 ,  G05F1/66 ,  G06F30/3308 ,  G06F30/367 ,  G06F2119/06

Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

公开(公告)号：US20240111350A1

公开(公告)日：2024-04-04

申请号：US17959931

申请日：2022-10-04

Applicant: Arm Limited

Inventor： Rainer Herberholz ,  Shidhartha Das

IPC: G06F1/30

CPC classification number: G06F1/305

Abstract: Various implementations described herein are directed to a device having core circuitry and hardware with functional paths and canary paths that are co-located with the functional paths. The device may have timing monitors that monitor and measure digital timing margins of the functional paths and the canary paths during droop events. Also, the device may have a control processor that sets-up parameters for hardware droop mitigation based on the digital timing margins, wherein the control processor calibrates the hardware for droop response or for adaptive clock and power control for droop mitigation based on the digital timing margins.

公开(公告)号：US20230289576A1

公开(公告)日：2023-09-14

申请号：US17689755

申请日：2022-03-08

Applicant: Arm Limited

Inventor： Fernando García Redondo ,  Mudit Bhargava ,  Paul Nicholas Whatmough ,  Shidhartha Das

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/082

Abstract: Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.

公开(公告)号：US11501150B2

公开(公告)日：2022-11-15

申请号：US16879587

申请日：2020-05-20

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Shidhartha Das ,  Fernando Garcia Redondo

IPC: G11C11/54 ,  G11C13/04 ,  G06N3/063 ,  G06N3/04

Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.

公开(公告)号：US11494256B2

公开(公告)日：2022-11-08

申请号：US17261217

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Milosch Meriac ,  Emre Özer ,  Xabier Iturbe ,  Balaji Venu ,  Shidhartha Das

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/30

Abstract: An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.

公开(公告)号：US20220179658A1

公开(公告)日：2022-06-09

申请号：US17674503

申请日：2022-02-17

Applicant: Arm Limited

Inventor： Matthew Mattina ,  Shidhartha Das ,  Glen Arnold Rosendale ,  Fernando Garcia Redondo

IPC: G06F9/38 ,  G06F7/487 ,  G06F7/544 ,  G06F9/30 ,  G06F17/16 ,  G06N3/06

Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.

公开(公告)号：US20220166436A1

公开(公告)日：2022-05-26

申请号：US17103585

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Benoit Labbe ,  Shidhartha Das ,  Thanusree Achuthan

IPC: H03L7/081 ,  H03L7/085 ,  G06F1/10 ,  G06F1/324

Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

公开(公告)号：US11334788B2

公开(公告)日：2022-05-17

申请号：US16315991

申请日：2017-06-14

Applicant: Arm Limited

Inventor： Shidhartha Das ,  Rune Holm

IPC: G06N3/06 ,  G06N3/04 ,  G11C11/54 ,  G06N3/063 ,  G11C13/00 ,  G06N3/08

Abstract: Broadly speaking, embodiments of the present techniques provide a reconfigurable hardware-based artificial neural network, wherein weights for each neural network node of the artificial neural network are obtained via training performed external to the neural network.

公开(公告)号：US20210295137A1

公开(公告)日：2021-09-23

申请号：US16822640

申请日：2020-03-18

Applicant: Arm Limited

Inventor： Urmish Ajit Thakker ,  Shidhartha Das ,  Ganesh Suryanarayan Dasika

IPC: G06N3/063 ,  G06N3/04 ,  G06F12/06

Abstract: The present disclosure advantageously provides a hybrid memory artificial neural network hardware accelerator that includes a communication bus interface, a static memory, a non-refreshed dynamic memory, a controller and a computing engine. The static memory stores at least a portion of an ANN model. The ANN model includes an input layer, one or more hidden layers and an output layer, ANN basis weights, input data and output data. The non-refreshed dynamic memory is configured to store ANN custom weights for the input, hidden and output layers, and output data. For each layer or layer portion, the computing engine generates the ANN custom weights based on the ANN basis weights, stores the ANN custom weights in the non-refreshed dynamic memory, executes the layer or layer portion, based on inputs and the ANN custom weights, to generate layer output data, and stores the layer output data.

公开(公告)号：US10810094B2

公开(公告)日：2020-10-20

申请号：US16014154

申请日：2018-06-21

Applicant: Arm Limited

Inventor： Milosch Meriac ,  Xabier Iturbe ,  Emre Ozer ,  Balaji Venu ,  Shidhartha Das

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/16 ,  G06F11/14 ,  G06F11/30 ,  G06F21/50

Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.