公开(公告)号：US07358601B1

公开(公告)日：2008-04-15

申请号：US11171488

申请日：2005-06-29

申请人： William C. Plants ,  John McCollum ,  Theodore Speers

发明人： William C. Plants ,  John McCollum ,  Theodore Speers

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H03K19/17732 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of second integrated circuit dice have logical function circuits disposed thereon and further have a second array of face-to-face bonding structures disposed on a first face thereof. The second array of face-to-face bonding structures of each member of the family mates with a different portion of the first array of face-to-face bonding structures.

摘要翻译： 集成电路系统包括第一集成电路管芯和第二集成电路管芯系列。 第一集成电路管芯具有设置在其上的输入/输出电路，并且还具有设置在其第一面上的面对面结合结构的第一阵列。 第二集成电路骰子族的每个成员具有设置在其上的逻辑功能电路，并且还具有设置在其第一面上的面对面结合结构的第二阵列。 该系列的每个构件的面对面结合结构的第二阵列与第一阵列的面对面结合结构的不同部分相配合。

公开(公告)号：US07872497B2

公开(公告)日：2011-01-18

申请号：US12645863

申请日：2009-12-23

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： H03K19/173 ,  G06F7/42 ,  G06F15/00

CPC分类号： G06F7/506 ,  H03K19/17728

摘要： A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

摘要翻译： 描述了用于集群现场可编程门阵列架构的快速，灵活的携带方案。 每个集群具有集群进位输入节点，集群进位输出节点，具有耦合到集群进位输出节点的输出的集群进位输出电路，耦合到集群进位输入节点的第一输入和第二输入和多个 每个逻辑模块包括耦合到进位电路的逻辑功能发生器电路。 逻辑模块以集群进位输入节点和集群携带输出电路的第二输入之间的串联进位装置耦合，使得算术逻辑电路的最低有效位可以可编程地置于任何逻辑模块中。

公开(公告)号：US20100244894A1

公开(公告)日：2010-09-30

申请号：US12794279

申请日：2010-06-04

申请人： Samuel W. Beal ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

发明人： Samuel W. Beal ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/17768 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

摘要翻译： 增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。 电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

公开(公告)号：US20100134142A1

公开(公告)日：2010-06-03

申请号：US12701068

申请日：2010-02-05

申请人： Gregory Bakker ,  Joel Landry ,  William C. Plants

发明人： Gregory Bakker ,  Joel Landry ,  William C. Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/1733 ,  G06F17/5054

摘要： A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the device. Provision is made for fourth instructions for saving a part of the internal logic state of the user logic programmed into the device into a non-volatile memory block and for fifth instructions for restoring a part of the internal logic state of the user logic programmed into the device from a non-volatile memory block. The device comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

摘要翻译： 一种用于可编程逻辑集成电路装置中的基于微控制器的控制系统的计算机可读介质中的计算机程序产品。 计算机程序产品包括用于初始化设备的第一指令，用于从可编程逻辑集成电路设备外部的数据源读取编程数据的第二指令，用于将编程数据传送到设备内部的控制元件中的第三指令。 提供了用于将编程到设备中的用户逻辑的内部逻辑状态的一部分保存到非易失性存储器块中的第四指令，以及用于恢复被编程到该非易失性存储器块中的用户逻辑的内部逻辑状态的一部分的第五指令 设备从非易失性存储器块。 该器件包括微控制器模块和具有编程电路的可编程逻辑模块，并且具有将微控制器模块耦合到编程电路的子总线。

公开(公告)号：US07663400B1

公开(公告)日：2010-02-16

申请号：US11962922

申请日：2007-12-21

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： H03K19/173 ,  G06F7/42 ,  G06F15/00

CPC分类号： G06F7/506 ,  H03K19/17728

摘要： A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

摘要翻译： 描述了用于集群现场可编程门阵列架构的快速，灵活的携带方案。 每个集群具有集群进位输入节点，集群进位输出节点，具有耦合到集群进位输出节点的输出的集群进位输出电路，耦合到集群进位输入节点的第一输入和第二输入和多个 每个逻辑模块包括耦合到进位电路的逻辑功能发生器电路。 逻辑模块以集群携带输入节点和集群携带输出电路的第二输入之间的串联进位布置耦合，使得算术逻辑电路的最低有效位可以可编程地置于任何逻辑模块中。

公开(公告)号：US07403411B1

公开(公告)日：2008-07-22

申请号：US11484243

申请日：2006-07-10

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.

摘要翻译： 一种用于为耐辐射静态随机存取存储器（SRAM）提供消旋电路的方法，包括：提供具有多个配置位的配置存储器; 将读和写电路耦合到配置存储器，用于配置多个配置位; 将辐射硬锁存器耦合到可编程元件，所述辐射硬锁存器控制所述可编程元件; 以及当所述写电路写入所述多个配置位中的至少一个配置位时，提供将所述多个配置位中的至少一个耦合到所述辐射硬锁存器的接口。

公开(公告)号：US07288957B2

公开(公告)日：2007-10-30

申请号：US11617559

申请日：2006-12-28

申请人： William C. Plants

发明人： William C. Plants

IPC分类号： H03K19/003

CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

公开(公告)号：US06791353B1

公开(公告)日：2004-09-14

申请号：US09819084

申请日：2000-09-25

申请人： Samuel W. Beal ,  Sinan Kaptonoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

发明人： Samuel W. Beal ,  Sinan Kaptonoglu ,  Jung-Cheun Lien ,  William Shu ,  King W. Chan ,  William C. Plants

IPC分类号： G06F738

CPC分类号： H03K19/17768 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

摘要翻译： 增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。 电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

公开(公告)号：US5698992A

公开(公告)日：1997-12-16

申请号：US746554

申请日：1996-11-13

申请人： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

发明人： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

IPC分类号： H03K19/177 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/173

CPC分类号： G01R31/2884 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17728

摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

摘要翻译： 用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。 包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。 互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。 包括本地互连通道的本地互连架构也被施加在阵列上。 每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

公开(公告)号：US5570041A

公开(公告)日：1996-10-29

申请号：US504051

申请日：1995-06-28

申请人： Khaled A. El-Avat ,  Sinan Kaptanoglu ,  King W. Chan ,  William C. Plants ,  Jung-Cheun Lien

发明人： Khaled A. El-Avat ,  Sinan Kaptanoglu ,  King W. Chan ,  William C. Plants ,  Jung-Cheun Lien

IPC分类号： H01L21/82 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/00 ,  H03K19/173 ,  H03K19/177

CPC分类号： G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.