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公开(公告)号:US12048212B2
公开(公告)日:2024-07-23
申请号:US17891211
申请日:2022-08-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yipeng Chen , Libin Liu , Yunfei Li
IPC: H10K59/12 , G09G3/3258 , H10K59/121 , H10K59/131 , H01L27/12
CPC classification number: H10K59/131 , G09G3/3258 , H10K59/1213 , H10K59/1216 , G09G2300/0842 , G09G2310/0262 , G09G2320/0209 , H01L27/124 , H01L27/1255
Abstract: Provided are a wiring structure of a pixel driving circuit, a display panel, and a display device. The wire layout includes: a first switching element, a second switching element and a driving transistor. A source electrode of the driving transistor is connected to a power signal line. The power signal line includes a first power signal line that is in a same direction as a data signal line, and the data signal line is arranged at a position of the first power signal line away from a gate electrode of the driving transistor.
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公开(公告)号:US12020651B2
公开(公告)日:2024-06-25
申请号:US18323476
申请日:2023-05-25
IPC: G09G3/3266 , G09G3/00 , G09G3/3233
CPC classification number: G09G3/3266 , G09G3/035 , G09G3/3233 , G09G2300/0804 , G09G2300/0842 , G09G2310/0221 , G09G2310/0286 , G09G2310/08 , G09G2320/0233 , G09G2330/023
Abstract: A display panel, a display device and a driving method are disclosed, the display panel includes a first display region and a second display region, the first display region includes rows of first pixel units, the second display region includes rows of second pixel units; the display panel further includes a first scan driving circuit for controlling the rows of first pixel units to emit light, and a second scan driving circuit for controlling the rows of second pixel units to emit light, and the driving method includes: providing a first start signal to the first scan driving circuit, and providing a second start signal to the second scan driving circuit; the second start signal and the first start signal are applied independently, respectively.
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公开(公告)号:US20240161669A1
公开(公告)日:2024-05-16
申请号:US17781988
申请日:2021-03-24
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jiangnan Lu , Guangliang Shang , Libin Liu , Long Han , Yu Feng
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0233 , G09G2330/021
Abstract: A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.
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公开(公告)号:US11903289B2
公开(公告)日:2024-02-13
申请号:US17948576
申请日:2022-09-20
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yipeng Chen , Lujiang Huangfu , Libin Liu
IPC: G09G3/3233 , H10K59/35 , H10K59/126 , H10K59/131 , H10K59/12
CPC classification number: H10K59/353 , G09G3/3233 , H10K59/126 , H10K59/131 , H10K59/352 , G09G2300/0452 , G09G2300/0842 , H10K59/1201
Abstract: A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.
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公开(公告)号:US11862646B2
公开(公告)日:2024-01-02
申请号:US17760988
申请日:2021-05-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Libin Liu , Can Zheng , Shiming Shi
CPC classification number: H01L27/124 , G06F3/0412 , G06F3/0443 , H01L27/1259 , G06F2203/04103 , G06F2203/04107
Abstract: Embodiments of the present disclosure provide a display substrate, a touch display panel and a display panel. The display substrate has a display region and a pin region on a side of the display region. The display substrate includes: a base substrate; and at least one first signal line and at least one second signal line both on a side of the base substrate and both extending to the display region from the pin region. The display substrate further includes a DC conductive structure connected to a constant DC voltage. The DC conductive structure is between the at least one first signal line and the at least one second signal line. Each of the at least one first signal line and the at least one second signal line is spaced apart from the DC conductive structure.
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公开(公告)号:US20230343285A1
公开(公告)日:2023-10-26
申请号:US17764395
申请日:2021-03-18
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jiangnan Lu , Guangliang Shang , Xinshe Yin , Libin Liu , Jianchao Zhu , Hao Zhang , Ke Feng
IPC: G09G3/3233 , G11C19/28
CPC classification number: G09G3/3233 , G11C19/28 , G09G2310/0286 , G09G2300/0842 , G09G2310/08
Abstract: A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.
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公开(公告)号:US11765943B2
公开(公告)日:2023-09-19
申请号:US17281606
申请日:2020-05-08
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Qian Yang , Lujiang Huangfu , Libin Liu
CPC classification number: H10K59/122 , G03F1/00 , G03F1/38 , H10K59/351 , H10K59/352 , H10K59/353 , H10K71/00 , H10K59/1201
Abstract: Provided are an array substrate and a manufacturing method therefor, a display device, and a mask plate. The array substrate includes a pixel defining layer having a first opening, a second opening, and a third opening passing through the pixel defining layer. Every two of the first to third openings are adjacent to each other. The pixel defining layer includes first to third opening denning portions. At least one of the ratio of the slope angle of a portion of the first opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion, and the ratio of the slope angle of a portion of the second opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion is from 0.8 to 1.25.
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公开(公告)号:US11587983B2
公开(公告)日:2023-02-21
申请号:US16959376
申请日:2019-07-31
Inventor: Kaipeng Sun , Yuanyou Qiu , Weiyun Huang , Yue Long , Chao Zeng , Jiangnan Lu , Libin Liu , Hongli Wang
IPC: H01L27/32
Abstract: An electroluminescent display panel includes a plurality of repeating units each including a first conductive layer, a first insulating layer including a first via hole, and an anode including a main body and an auxiliary portion. At least one repeating unit includes a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel; the area of the main body of the third-color sub-pixel is larger than that of the second-color sub-pixel and that of the first-color sub-pixel; and an overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the second-color sub-pixel and the first conductive layer, and the overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the first-color sub-pixel and the first conductive layer.
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公开(公告)号:US11580888B2
公开(公告)日:2023-02-14
申请号:US17414126
申请日:2020-10-19
Applicant: BOE Technology Group Co., Ltd.
IPC: G09G3/00 , G09G3/3233 , H01L29/786 , H01L27/32 , H01L51/00
Abstract: A stretchable display panel, a method for compensating a threshold voltage of a transistor in the stretchable display panel, and a computer readable storage medium. The stretchable display panel includes: a base substrate; a transistor on the base substrate, the transistor includes a gate electrode layer and an active layer that are at least partially stacked; and a voltage compensation layer, the voltage compensation layer is located between the transistor and the base substrate, wherein the voltage compensation layer is applied with a compensation voltage that depends on a stretching amount of the stretchable display panel.
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公开(公告)号:US11574597B2
公开(公告)日:2023-02-07
申请号:US17426949
申请日:2020-10-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Can Zheng , Yu Feng , Guangliang Shang , Libin Liu , Shiming Shi
IPC: G09G3/3266 , G09G3/20
Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.
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