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公开(公告)号：US12094409B2
公开(公告)日：2024-09-17
申请号：US18044114
申请日：2021-02-07
Inventor： Hongfei Cheng , Xueguang Hao
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/08 , G09G2320/0223 , G09G2320/0233 , G09G2320/045
Abstract: Embodiments of the present disclosure provide a pixel circuitry, a drive method thereof, an array substrate and a display panel. The pixel circuitry may comprise a drive circuit, a data write circuit, an initialization circuit, a first light emission control circuit, a first storage circuit, a second storage circuit and a second light emission control circuit. The drive circuit may be coupled to a first node, a second node and a third node, and may provide a drive current to a light emitting device. The first storage circuit may store a voltage difference between the first voltage signal terminal and the second node. The second storage circuit may store a voltage difference between the first node and the second node.
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公开(公告)号：US12092934B2
公开(公告)日：2024-09-17
申请号：US17890451
申请日：2022-08-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei Cheng , Jianbo Xian
IPC: H01L27/12 , G02B30/27 , G02F1/13 , G02F1/1362 , G02F1/1368 , G02F1/136
CPC classification number: G02F1/136286 , G02B30/27 , G02F1/13 , G02F1/136227 , G02F1/1368 , H01L27/1222 , H01L27/124 , G02F1/13606 , G02F2201/123
Abstract: An array substrate and a display device are disclosed. The array substrate includes a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a pixel electrode arranged in a region defined by an adjacent gate line and an adjacent data line, and a thin film transistor arranged at an intersection of the gate lines and the data lines. A drain of the thin film transistor is connected with the pixel electrode through a via hole. The gate lines further include a widening portion between adjacent data lines. The widening portion comprises a recess structure. An orthogonal projection of the recess structure on the base substrate at least partly overlaps that of the drain of the thin film transistor on the base substrate.
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43.发明授权公开(公告)号：US11943979B2
公开(公告)日：2024-03-26
申请号：US17706901
申请日：2022-03-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei Cheng
IPC: H10K59/131 , H01L27/02 , H10K59/12
CPC classification number: H10K59/131 , H01L27/0296 , H10K59/1201
Abstract: An array substrate and a fabrication method thereof, an array substrate motherboard, and a display device are disclosed. The array substrate includes a display region and a bonding region outside the display region. The array substrate further includes: a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region; and an electrostatic barrier line, the electrostatic barrier line has one end electrically connected with the bonding electrode, and the other end extends to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is greater than resistivity of the bonding electrode.
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公开(公告)号：US11906859B2
公开(公告)日：2024-02-20
申请号：US18129252
申请日：2023-03-31
Inventor： Hongfei Cheng , Hui Li
IPC: G02F1/1345 , G02F1/1362 , H01L27/02 , H10K59/131
CPC classification number: G02F1/1345 , G02F1/13452 , G02F1/136204 , G02F1/136254 , G02F1/136286 , H01L27/0288 , H10K59/131
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, and a transistor, an anti-static wire, a first anti-static resistor and a first ground bonding pad on the base substrate, wherein a first terminal of the first anti-static resistor is electrically connected to a first end of the anti-static wire, a second terminal of the first anti-static resistor is electrically connected to the first ground bonding pad, and the first anti-static resistor is at a different layer from a layer at which the anti-static wire is located and a layer at which the first ground bonding pad is located, and is at a same layer as an active layer of the resistor.
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45.发明授权公开(公告)号：US11803088B2
公开(公告)日：2023-10-31
申请号：US17046820
申请日：2020-03-26
Inventor： Hongfei Cheng , Jianbo Xian , Hui Li
IPC: G02F1/1362 , G02F1/1343 , H01L27/12
CPC classification number: G02F1/136204 , G02F1/1343 , H01L27/1222
Abstract: The disclosure relates to the technical field of display, and discloses an electrode structure, a capacitor, a GOA circuit, an array substrate, a display panel and a display device, wherein the electrode structure includes a body and a first opening formed in the body, the first opening has a half-enclosed shape, and a part, enclosed by the first opening, of the body has a tip structure. Each of the capacitor, the GOA circuit, the array substrate, the display panel and the display device includes the above-mentioned electrode structure.
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Patent Agency Ranking
公开(公告)号：US11783743B2
公开(公告)日：2023-10-10
申请号：US17416459
申请日：2020-12-28
Inventor： Hongfei Cheng
IPC: G09G3/20 , G09G3/3266 , G09G3/36 , G11C19/28
CPC classification number: G09G3/20 , G09G3/3266 , G09G3/3677 , G11C19/28 , G09G2310/0267 , G09G2310/0286
Abstract: A shifting register, a driving method thereof, a driving circuit and a display device are provided. The shifting register includes a control circuit (10), a first output circuit (20), a second output circuit (30) and a first switching transistor (T1). Shifting output of signals may be realized through interaction of all of the circuits. Moreover, an influence of a leak current on a signal of a second end of the first switching transistor is reduced by setting the first switching transistor (T1) to isolate the second output circuit (30) and a second node (N2).
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公开(公告)号：US11515337B2
公开(公告)日：2022-11-29
申请号：US16771038
申请日：2019-06-25
Inventor： Hongfei Cheng
IPC: H01L27/12
Abstract: An array substrate having a plurality of subpixels is provided. In a respective one of the plurality of subpixels, the array substrate includes a base substrate; and a thin film transistor on the base substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The drain electrode includes a first portion, a second portion, and a third portion connecting the first portion and the second portion. An orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of a first gate line protrusion of a respective one of the plurality of gate lines on the base substrate. An orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of a second gate line protrusion of the respective one of the plurality of gate lines on the base substrate.
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公开(公告)号：US11231606B2
公开(公告)日：2022-01-25
申请号：US15776226
申请日：2017-11-15
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei Cheng , Yuxin Zhang
IPC: G02F1/1333 , C08K3/04
Abstract: Embodiments of the present invention provide a conductive substrate, a manufacturing method thereof and a display device. The conductive substrate includes a base substrate and a first conductive layer and a second conductive layer disposed on the base substrate, wherein the first conductive layer and the second conductive layer contact with each other, the first conductive layer is configured to be electrically connected with separated parts after the second conductive layer is fractured, and the first conductive layer includes a composite material layer or a nanowire conductive network layer.
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公开(公告)号：US11221524B2
公开(公告)日：2022-01-11
申请号：US16369553
申请日：2019-03-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wenbo Li , Xinyin Wu , Pan Li , Hongfei Cheng , Jianbo Xian
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L27/12 , H01L21/02 , H01L21/285 , H01L21/443 , H01L27/06 , H01L29/49 , H01L29/66 , H01L27/02 , H01L29/51 , H01L29/786
Abstract: The present application discloses an array substrate, a display panel and a display device. The array substrate comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, the pixel unit further comprising: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.
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公开(公告)号：US20210408056A1
公开(公告)日：2021-12-30
申请号：US16771038
申请日：2019-06-25
Inventor： Hongfei Cheng
IPC: H01L27/12
Abstract: An array substrate having a plurality of subpixels is provided. In a respective one of the plurality of subpixels, the array substrate includes a base substrate; and a thin film transistor on the base substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The drain electrode includes a first portion, a second portion, and a third portion connecting the first portion and the second portion. An orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of a first gate line protrusion of a respective one of the plurality of gate lines on the base substrate. An orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of a second gate line protrusion of the respective one of the plurality of gate lines on the base substrate.
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