METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES
    41.
    发明申请
    METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES 有权
    在不同结构上形成不同厚度硅的方法

    公开(公告)号:US20080286921A1

    公开(公告)日:2008-11-20

    申请号:US11748743

    申请日:2007-05-15

    CPC classification number: H01L21/324 H01L21/28052 H01L29/66507 H01L29/78

    Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

    Abstract translation: 形成器件的栅极和有源区,并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅,同时保持覆盖有氮化物的其它区域中的硅或多晶硅。 金属层沉积在暴露的硅或多晶硅上,退火在所选择的暴露区域中形成硅化物层。 氧化物层和/或氮化物层从被覆盖区域移除,另一个金属层被沉积​​。 在第二暴露区域上形成一层厚度的硅化物,并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。

    Method of detecting bladder urothelial carcinoma
    42.
    发明申请
    Method of detecting bladder urothelial carcinoma 审中-公开
    检测膀胱尿路上皮癌的方法

    公开(公告)号:US20080003609A1

    公开(公告)日:2008-01-03

    申请号:US11801676

    申请日:2007-05-10

    Applicant: Bin Yang

    Inventor: Bin Yang

    CPC classification number: C12Q1/6886 C12Q2600/112 C12Q2600/154 C12Q2600/16

    Abstract: A diagnostic method for bladder urethelial carcinoma includes obtaining an isolated nucleotide sample from a subject and detecting the promoter methylation of at least three tumor suppressor genes selected form group consisting of DAPK, RAR-beta, p14, p73, MGMT, APC, SOCS-1, BRCA-1, and FHIT.

    Abstract translation: 膀胱尿道上皮癌的诊断方法包括从受试者获得分离的核苷酸样品,并检测至少三种选自DAPK,RAR-β,p14,p73,MGMT,APC,SOCS-1的肿瘤抑制基因的启动子甲基化 ,BRCA-1和FHIT。

    Glucagon antagonists
    46.
    发明授权
    Glucagon antagonists 有权
    胰高血糖素拮抗剂

    公开(公告)号:US08981047B2

    公开(公告)日:2015-03-17

    申请号:US12739342

    申请日:2008-10-23

    CPC classification number: C07K14/605 A61K38/00

    Abstract: Glucagon antagonists are provided which comprise amino acid substitutions and/or chemical modifications to glucagon sequence. In one embodiment, the glucagon antagonists comprise a native glucagon peptide that has been modified by the deletion of the first two to five amino acid residues from the N-terminus and (i) an amino acid substitution at position 9 (according to the numbering of native glucagon) or (ii) substitution of the Phe at position 6 (according to the numbering of native glucagon) with phenyl lactic acid (PLA). In another embodiment, the glucagon antagonists comprise the structure A-B-C as described herein, wherein A is PLA, an oxy derivative thereof, or a peptide of 2-6 amino acids in which two consecutive amino acids of the peptide are linked via an ester or ether bond.

    Abstract translation: 提供了包含对胰高血糖素序列的氨基酸取代和/或化学修饰的胰高血糖素拮抗剂。 在一个实施方案中,胰高血糖素拮抗剂包含通过从N-末端缺失前两个至五个氨基酸残基而修饰的天然胰高血糖素肽,以及(i)在第9位的氨基酸取代(根据 天然胰高血糖素)或(ii)用苯基乳酸(PLA)取代第6位的Phe(根据天然胰高血糖素的编号)。 在另一个实施方案中,胰高血糖素拮抗剂包含如本文所述的结构ABC,其中A是PLA,其氧衍生物或2-6个氨基酸的肽,其中肽的两个连续氨基酸经由酯或醚连接 键。

    Use of band edge gate metals as source drain contacts
    48.
    发明授权
    Use of band edge gate metals as source drain contacts 有权
    使用带边栅极金属作为源极漏极触点

    公开(公告)号:US08741753B2

    公开(公告)日:2014-06-03

    申请号:US13611736

    申请日:2012-09-12

    Abstract: A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

    Abstract translation: 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层,覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture
    50.
    发明授权
    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture 有权
    具有均匀薄的硅化物层的MOSFET集成电路及其制造方法

    公开(公告)号:US08652963B2

    公开(公告)日:2014-02-18

    申请号:US13237732

    申请日:2011-09-20

    CPC classification number: H01L29/665 H01L21/28518 H01L29/6659 H01L29/7833

    Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

    Abstract translation: 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时,除去过量的(未反应的)金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层,其在宽和窄接触沟槽的底部显示均匀的厚度。

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