公开(公告)号：US20080286921A1

公开(公告)日：2008-11-20

申请号：US11748743

申请日：2007-05-15

申请人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

发明人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

IPC分类号： H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28052 ,  H01L29/66507 ,  H01L29/78

摘要： The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

摘要翻译： 形成器件的栅极和有源区，并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅，同时保持覆盖有氮化物的其它区域中的硅或多晶硅。 金属层沉积在暴露的硅或多晶硅上，退火在所选择的暴露区域中形成硅化物层。 氧化物层和/或氮化物层从被覆盖区域移除，另一个金属层被沉积​​。 在第二暴露区域上形成一层厚度的硅化物，并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。

公开(公告)号：US08236693B2

公开(公告)日：2012-08-07

申请号：US11748743

申请日：2007-05-15

申请人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

发明人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

IPC分类号： H01L21/44

CPC分类号： H01L21/324 ,  H01L21/28052 ,  H01L29/66507 ,  H01L29/78

摘要： The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

摘要翻译： 形成器件的栅极和有源区，并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅，同时保持覆盖有氮化物的其它区域中的硅或多晶硅。 金属层沉积在暴露的硅或多晶硅上，退火在所选择的暴露区域中形成硅化物层。 氧化物层和/或氮化物层从被覆盖区域移除，另一个金属层被沉积​​。 在第二暴露区域上形成一层厚度的硅化物，并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。

公开(公告)号：US06258683B1

公开(公告)日：2001-07-10

申请号：US09477741

申请日：2000-01-05

申请人： Paul Besser ,  Simon S. Chan ,  Yowjuang Bill Liu

发明人： Paul Besser ,  Simon S. Chan ,  Yowjuang Bill Liu

IPC分类号： H01L21336

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and arrangement for forming a local interconnect without etching completely through a junction and causing device shorts introduces an additional ion implantation step following the etching of the local interconnect opening into the substrate. The additional ion implantation step into the active region ensures that the depth of the junction is below the depth reached by the local interconnect opening and the substrate.

摘要翻译： 用于形成局部互连而不是完全蚀刻通过结而导致器件短路的局部互连的方法和装置在蚀刻到衬底中的局部互连开口之后引入额外的离子注入步骤。 进入有源区域的附加离子注入步骤确保结的深度低于局部互连开口和衬底达到的深度。

公开(公告)号：US08314454B2

公开(公告)日：2012-11-20

申请号：US12970687

申请日：2010-12-16

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

公开(公告)号：US07144818B2

公开(公告)日：2006-12-05

申请号：US10729479

申请日：2003-12-05

申请人： Mario M. Pelella ,  Simon S. Chan

发明人： Mario M. Pelella ,  Simon S. Chan

IPC分类号： H01L21/311

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。 衬底利用基层中的沟槽以在层中引起应力。 衬底可以包括硅。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US06291339B1

公开(公告)日：2001-09-18

申请号：US09225218

申请日：1999-01-04

申请人： Steven C. Avanzino ,  Simon S. Chan

发明人： Steven C. Avanzino ,  Simon S. Chan

IPC分类号： H01L214263

CPC分类号： H01L21/76819

摘要： A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.

摘要翻译： 具有旋转低k间隙填充层的双层层间电介质用较高的k电介质层封装。 在封盖之前，由于图案密度对纺丝低k电介质层的厚度的影响，使旋转低k电介质层平坦化以减少或消除层的相对厚度的系统变化。 通过去除低k电介质层和覆盖层的相对厚度的变化，均匀厚的复合层间电介质的有效介电常数与电路上的位置无关，防止电路速度的差异和时钟偏差的产生 电路。

公开(公告)号：US6093635A

公开(公告)日：2000-07-25

申请号：US993124

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

发明人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。 在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

公开(公告)号：US4808273A

公开(公告)日：1989-02-28

申请号：US192343

申请日：1988-05-10

申请人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

发明人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

IPC分类号： H01L21/74 ,  H01L21/768 ,  C25D5/02

CPC分类号： H01L21/76898

摘要： A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.

摘要翻译： 公开了一种用于在半导体晶片中形成完全金属化的通孔的方法。 金属焊盘与导电互连网络一起形成在半导体晶片的一个面上。 然后沉积绝缘层以覆盖晶片的这个面。 孔在晶片的相对表面被蚀刻，直至并暴露出金属焊盘的一部分。 然后使用金属垫作为阴极，通过电镀将通孔用金属完全填充。

公开(公告)号：US07879718B2

公开(公告)日：2011-02-01

申请号：US11616544

申请日：2006-12-27

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L21/44

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

摘要翻译： 提供一种用于在半导体存储器件中形成互连的方法。 该方法包括在衬底上形成一对源极选择晶体管。 源区域形成在一对源极选择晶体管之间的衬底中。 在所述一对源极选择晶体管之间形成第一层间电介质。 掩模层沉积在一对源极选择晶体管和层间电介质上，其中掩模层限定了一对源极选择晶体管之间的局部互连区域，其宽度小于一对源选择晶体管之间的距离。 蚀刻半导体存储器件以去除局部互连区域中的第一层间电介质的一部分，从而暴露源极区域。 在局部互连区域中形成金属接触。

公开(公告)号：US07538383B1

公开(公告)日：2009-05-26

申请号：US11416703

申请日：2006-05-03

申请人： Meng Ding ,  Simon S. Chan

发明人： Meng Ding ,  Simon S. Chan

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568

摘要： According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.

摘要翻译： 根据一个示例性实施例，两比特存储器单元包括位于衬底上方的栅极堆叠，其中栅极堆叠包括电荷捕获层。 电荷捕获层包括第一和第二导电段和氮化物区段，其中氮化物区段位于第一和第二导电区段之间。 氮化物区段将第一导电段与第二导电段电绝缘。 第一和第二导电段在双位存储单元中提供相应的第一和第二数据位存储单元。 栅极堆叠还可以包括位于衬底和电荷俘获层之间的较低氧化物段。 栅极堆叠还可以包括位于电荷捕获层上方的上部氧化物段。 栅极堆叠可以位于第一介电段和第二介电段之间，其中第一和第二介电段位于相应的第一和第二位线之上。