公开(公告)号：US08749067B2

公开(公告)日：2014-06-10

申请号：US13132985

申请日：2011-02-23

申请人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

发明人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76847 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括接触插塞，其包括由布置在源区和漏区上的第一阻挡层和布置在第一阻挡层上的钨层形成的第一接触插塞; 以及第二接触插塞，其包括布置在金属栅极和第一接触插塞两者上的第二阻挡层和布置在第二阻挡层上的导电层。 导电层的导电性高于钨层。 还提供了一种用于形成半导体器件的方法。 本发明提供了当使用铜接触技术时提高器件的可靠性的优点。

公开(公告)号：US08703567B2

公开(公告)日：2014-04-22

申请号：US13497744

申请日：2011-11-29

申请人： Guilei Wang ,  Chunlong Li ,  Chao Zhao

发明人： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/66651 ,  H01L29/7833

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; forming a semiconductor device structure in and above the active region layer; characterized in that the carrier mobility of the active region layer is higher than that of the substrate. Said active region is formed of a material different from that of the substrate, the carrier mobility in the channel region is enhanced, thereby the device response speed is improved and the device performance is enhanced. Unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在衬底上形成绝缘隔离层; 在绝缘隔离层中形成绝缘隔离层沟槽; 在绝缘隔离层沟槽中形成有源区; 在有源区域层中形成半导体器件结构; 其特征在于，有源区层的载流子迁移率高于基板的载流子迁移率。 所述有源区由不同于衬底的材料形成，通道区域中的载流子迁移率增强，从而提高了器件响应速度并提高了器件性能。 与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US20130313655A1

公开(公告)日：2013-11-28

申请号：US13878524

申请日：2012-07-18

申请人： Guilei Wang ,  Hushan Cui ,  Chao Zhao

发明人： Guilei Wang ,  Hushan Cui ,  Chao Zhao

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7846 ,  H01L29/045 ,  H01L29/66553 ,  H01L29/66636

摘要： A semiconductor device comprises a substrate; a shallow trench isolation embedded in the substrate and forms at least one opening region; a channel region located in the opening region; a gate stack including a gate dielectric layer and a gate electrode layer, located above said channel region; a source/drain region located on both sides of the channel region, including a stress layer which provides strain for the channel region. A liner layer is provided between the shallow trench isolation and the stress layer, which serves as a crystal seed layer of the stress layer. A liner layer and a pad oxide layer are provided between the substrate and the shallow trench isolation. The liner layer is inserted between the STI and the stress layer of the source/drain region as a crystal seed layer or nucleating layer for epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering.

摘要翻译： 半导体器件包括衬底; 嵌入衬底中的浅沟槽隔离物并形成至少一个开口区域; 位于所述开口区域中的通道区域; 包括位于所述沟道区上方的栅极介质层和栅极电极层的栅极堆叠; 位于沟道区两侧的源/漏区，包括为沟道区提供应变的应力层。 衬底层设置在浅沟槽隔离层和应力层之间，其作为应力层的晶种子层。 衬底层和衬垫氧化物层设置在衬底和浅沟槽隔离之间。 衬垫层作为晶种层或用于外延生长的成核层插入到STI和源极/漏极区的应力层之间，从而消除了源极/漏极应变工程中的STI边缘效应。

公开(公告)号：US20130241004A1

公开(公告)日：2013-09-19

申请号：US13520618

申请日：2012-04-11

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是 增强。

公开(公告)号：US20120178255A1

公开(公告)日：2012-07-12

申请号：US13377889

申请日：2011-04-20

申请人： Tao Yang ,  Chao Zhao ,  Junfong Li

发明人： Tao Yang ,  Chao Zhao ,  Junfong Li

IPC分类号： H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/32135

摘要： A method for improving the within die uniformity of the metal plug CMP process in the gate last route is provided. Before performing the CMP process for forming the metal plug, a metal etching process is applied, so that the step height between the metal layers in the contact hole area and the non-contact hole area is greatly reduced. Therefore, the relatively small step height will exert a significantly less effect on the following CMP process, so that the step height will be limitedly transferred to the top of metal plug after finishing CMP process. In this way, the recess on top of the metal plug is largely reduced, so that a flat top of the metal plug is obtained, and within die uniformity and electrical properties the device are improved.

摘要翻译： 提供了一种用于提高门最后路线中的金属塞CMP工艺的模内均匀性的方法。 在进行用于形成金属插塞的CMP处理之前，应用金属蚀刻工艺，使得接触孔区域中的金属层与非接触孔区域之间的台阶高度大大降低。 因此，相对较小的台阶高度将对下列CMP工艺产生显着影响较小，因此在完成CMP工艺后，台阶高度将有限地转移到金属插头的顶部。 以这种方式，金属插头顶部的凹槽大大减小，从而获得金属插头的平坦的顶部，并且在模具的均匀性和电气特性中改进了该装置。

公开(公告)号：US20100207177A1

公开(公告)日：2010-08-19

申请号：US12641945

申请日：2009-12-18

申请人： Chung-Shi Liu ,  Gerald Beyer ,  Steven Demuynck ,  Zsolt Tokei ,  Roger Palmans ,  Chao Zhao ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Gerald Beyer ,  Steven Demuynck ,  Zsolt Tokei ,  Roger Palmans ,  Chao Zhao ,  Chen-Hua Yu

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.

摘要翻译： 公开了一种通过集成电路的前金属电介质（PMD）层之间的线的前端和后端之间产生接触的方法以及由此制造的器件。 PMD层包括氧气。 一方面，该方法包括在PMD中产生孔，在孔的底部沉积导电阻挡层，在孔的底部和侧壁上沉积CuMn合金，用Cu填充孔的剩余部分。 所述方法还包括进行退火处理以在所述孔的侧壁上形成阻挡层，其中所述势垒具有包括Mn的氧化物。 该方法还包括执行CMP处理。

公开(公告)号：US20140227878A1

公开(公告)日：2014-08-14

申请号：US14342421

申请日：2012-03-05

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Yihong Lu

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Yihong Lu

IPC分类号： H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/28123 ,  H01L21/31111 ,  H01L29/66795 ,  H01L29/785

摘要： A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost.

摘要翻译： 一种制造小尺寸鳍状结构的方法，包括：依次在基板上形成第一掩模层和第二掩模层; 蚀刻第一掩模层和第二掩模层以形成硬掩模图案，其中第二掩模层图案比第一掩模层图案宽; 消除第二掩模层图案; 并且通过以第一掩模层图案作为掩模来进行基板的干蚀刻，以便形成鳍状结构。 根据本发明的小型翅片状结构体的制造方法，首先制作大尺寸的硬掩模，然后通过湿式腐蚀制备宽度可控的小尺寸硬掩模，最后制成体硅 晶片被蚀刻，从而获得所需的小尺寸鳍状结构，从而提高了器件的电气特性和集成度，简化了工艺并降低了成本。

公开(公告)号：US08779475B2

公开(公告)日：2014-07-15

申请号：US13582432

申请日：2011-11-28

申请人： Guilei Wang ,  Chunlong Li ,  Chao Zhao

发明人： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC分类号： H01L27/085 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51 ,  H01L21/8258 ,  H01L29/20 ,  H01L21/8238 ,  H01L21/28

CPC分类号： H01L29/78 ,  H01L21/02532 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/51 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

摘要翻译： 本发明公开了一种半导体器件，包括：衬底，形成在衬底上的绝缘隔离层，形成在绝缘隔离层中的第一有源区和第二有源区，其特征在于，第一有源区 区域层和/或第二有源区层比衬底高。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区，增加沟道区中的载流子迁移率，从而显着改善器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US08541296B2

公开(公告)日：2013-09-24

申请号：US13510730

申请日：2011-11-30

申请人： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

发明人： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/51

摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

摘要翻译： 本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。 根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。 它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

公开(公告)号：US08501500B2

公开(公告)日：2013-08-06

申请号：US13499288

申请日：2011-11-29

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L29/66545

摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.

摘要翻译： 本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。 根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈， 准确地不会对晶片造成任何损坏。