公开(公告)号：US20120043592A1

公开(公告)日：2012-02-23

申请号：US13132985

申请日：2011-02-23

申请人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

发明人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76847 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括接触插塞，其包括由布置在源区和漏区上的第一阻挡层和布置在第一阻挡层上的钨层形成的第一接触插塞; 以及第二接触插塞，其包括布置在金属栅极和第一接触插塞两者上的第二阻挡层和布置在第二阻挡层上的导电层。 导电层的导电性高于钨层。 还提供了一种用于形成半导体器件的方法。 本发明提供了当使用铜接触技术时提高器件的可靠性的优点。

公开(公告)号：US08749067B2

公开(公告)日：2014-06-10

申请号：US13132985

申请日：2011-02-23

申请人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

发明人： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76847 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括接触插塞，其包括由布置在源区和漏区上的第一阻挡层和布置在第一阻挡层上的钨层形成的第一接触插塞; 以及第二接触插塞，其包括布置在金属栅极和第一接触插塞两者上的第二阻挡层和布置在第二阻挡层上的导电层。 导电层的导电性高于钨层。 还提供了一种用于形成半导体器件的方法。 本发明提供了当使用铜接触技术时提高器件的可靠性的优点。

公开(公告)号：US08410541B2

公开(公告)日：2013-04-02

申请号：US12935364

申请日：2010-06-24

申请人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

发明人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.

摘要翻译： 提供了具有通过接口偶极子控制的阈值电压的CMOSFET器件及其制造方法。 覆盖层，例如非常薄的多晶硅，非晶硅或SiO 2层被插入在CMOSFET器件的高k栅极电介质层的内部，并且阈值电压通过由 盖层在高k栅介质层内。 根据本发明，可以有效地优化CMOSFET器件的阈值电压而不显着增加其EOT。

公开(公告)号：US20110169097A1

公开(公告)日：2011-07-14

申请号：US12937444

申请日：2010-06-24

申请人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

发明人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; an interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer. According to to the present invention, the very thin metal layers are deposited between the high-k gate dielectric layers for NMOS and PMOS devices respectively, such that a flat band voltage of the device is adjusted by means of positive or negative charges generated by the metal layers inside the high-k gate dielectric layers, and thus the threshold voltage of the device is controlled. Thus, it is possible not only to is enhance interface dipoles between the high-k dielectric layers and the SiO2 interface layer, but also to well control types and amounts of fixed charges inside the high-k gate dielectric layers, so as to effectively control the threshold voltage of the device.

摘要翻译： 提供了具有通过其栅极堆叠配置控制的阈值电压的CMOSFET器件及其制造方法。 CMOSFET器件包括：半导体衬底; 在硅衬底上生长的界面层; 沉积在界面层上的第一高k栅介质层; 沉积在第一高k栅极电介质层上的非常薄的金属层; 沉积在金属层上的第二高k栅介质层; 以及沉积在第二高k栅极电介质层上的栅电极层。 根据本发明，非常薄的金属层分别沉积在用于NMOS和PMOS器件的高k栅极电介质层之间，使得器件的平带电压通过由 金属层在高k栅极电介质层内，因此控制器件的阈值电压。 因此，不仅可以增强高k电介质层和SiO 2界面层之间的界面偶极子，而且可以很好地控制高k栅极电介质层内的固定电荷的类型和量，以有效地控制 器件的阈值电压。

公开(公告)号：US08703558B2

公开(公告)日：2014-04-22

申请号：US13140141

申请日：2011-02-24

申请人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Xinyu Liu ,  Huilong Zhu

发明人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Xinyu Liu ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/778 ,  H01L29/1606 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

摘要翻译： 本发明提供了一种石墨烯器件结构及其制造方法，该器件结构包括石墨烯层; 与石墨烯层接触的栅极区域; 半导体掺杂区域形成在栅极区域的两个相对侧并与石墨烯层接触，其中半导体掺杂区域与栅极区域隔离; 在栅极区域上形成的触点和形成在半导体掺杂区域上的触点。 通过半导体掺杂区域增加石墨烯器件的开关比，而不增加石墨烯材料的带隙，即不影响材料的迁移率或器件的速度，从而增加石墨烯材料的适用性 在CMOS设备中。

公开(公告)号：US20120104506A1

公开(公告)日：2012-05-03

申请号：US12935364

申请日：2010-06-24

申请人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Depeng Chen

发明人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Depeng Chen

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L29/513 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.

摘要翻译： 提供了具有通过接口偶极子控制的阈值电压的CMOSFET器件及其制造方法。 覆盖层，例如非常薄的多晶硅，非晶硅或SiO 2层被插入在CMOSFET器件的高k栅极电介质层的内部，并且阈值电压通过由 盖层在高k栅介质层内。 根据本发明，可以有效地优化CMOSFET器件的阈值电压而不显着增加其EOT。

公开(公告)号：US08410555B2

公开(公告)日：2013-04-02

申请号：US12937444

申请日：2010-06-24

申请人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

发明人： Wenwu Wang ,  Huilong Zhu ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L27/12

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.

摘要翻译： 提供了具有通过其栅极堆叠配置控制的阈值电压的CMOSFET器件及其制造方法。 CMOSFET器件包括：半导体衬底; 在硅衬底上生长的界面层; 沉积在界面层上的第一高k栅介质层; 沉积在第一高k栅极电介质层上的非常薄的金属层; 沉积在非常薄的金属层上的第二高k栅介质层; 以及沉积在第二高k栅极电介质层上的栅电极层。

公开(公告)号：US08329566B2

公开(公告)日：2012-12-11

申请号：US12922391

申请日：2010-06-22

申请人： Huilong Zhu ,  Wenwu Wang

发明人： Huilong Zhu ,  Wenwu Wang

IPC分类号： H01L21/336 ,  H01L21/36 ,  H01L21/20 ,  H01L21/04 ,  H01L21/425

CPC分类号： H01L29/105 ,  H01L21/2652 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.

摘要翻译： 本发明涉及一种制造半导体器件的方法，其中所述方法包括：提供衬底; 在基板上形成源极区域，漏极区域，虚拟栅极结构和栅极电介质层，其中，虚设栅极结构位于基板上的源极区域和漏极区域之间，栅极介电层位于基板 和虚拟门结构; 对源极区域和漏极区域进行退火; 去除虚拟栅极结构以形成开口; 从开口将掺杂剂注入到基底中以形成陡峭的退浆井; 退火以激活掺杂剂; 以及通过沉积在栅介质层上形成金属栅极。

公开(公告)号：US20120097923A1

公开(公告)日：2012-04-26

申请号：US13140141

申请日：2011-02-24

申请人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Xinyu Liu ,  Huilong Zhu

发明人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Xinyu Liu ,  Huilong Zhu

IPC分类号： H01L29/786 ,  H01L29/165 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/778 ,  H01L29/1606 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

摘要翻译： 本发明提供了一种石墨烯器件结构及其制造方法，该器件结构包括石墨烯层; 与石墨烯层接触的栅极区域; 半导体掺杂区域形成在栅极区域的两个相对侧并与石墨烯层接触，其中半导体掺杂区域与栅极区域隔离; 在栅极区域上形成的触点和形成在半导体掺杂区域上的触点。 通过半导体掺杂区域增加石墨烯器件的开关比，而不增加石墨烯材料的带隙，即不影响材料的迁移率或器件的速度，从而增加石墨烯材料的适用性 在CMOS设备中。

公开(公告)号：US20110256683A1

公开(公告)日：2011-10-20

申请号：US12922391

申请日：2010-06-22

申请人： Huilong Zhu ,  Wenwu Wang

发明人： Huilong Zhu ,  Wenwu Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/105 ,  H01L21/2652 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.

摘要翻译： 本发明涉及一种制造半导体器件的方法，其中所述方法包括：提供衬底; 在基板上形成源极区域，漏极区域，虚拟栅极结构和栅极电介质层，其中，虚设栅极结构位于基板上的源极区域和漏极区域之间，栅极电介质层位于基板 和虚拟门结构; 对源极区域和漏极区域进行退火; 去除虚拟栅极结构以形成开口; 从开口将掺杂剂注入到基底中以形成陡峭的退浆井; 退火以激活掺杂剂; 以及通过沉积在栅介质层上形成金属栅极。