公开(公告)号：US20080230844A1

公开(公告)日：2008-09-25

申请号：US11688592

申请日：2007-03-20

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653

摘要： A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

摘要翻译： 提供了一种用于形成具有减小的源极/漏极延伸寄生电阻的半导体器件的系统和方法。 一个实施例包括在形成硅化物接触之后，将两种金属（例如用于NMOS晶体管的镱和镍或用于PMOS晶体管的铂和镍）注入到源极/漏极延伸部中。 然后进行退火以在源极/漏极延伸部内产生第二硅化物区域。 任选地，可以在第二硅化物区域上进行第二退火以迫使进一步的反应。 该过程可以对同一衬底上的多个半导体器件执行。

公开(公告)号：US08110890B2

公开(公告)日：2012-02-07

申请号：US11758043

申请日：2007-06-05

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

IPC分类号： H01L21/70

CPC分类号： H01L21/76202 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

摘要翻译： 包括可折入隔离结构的半导体器件和用于制造这种器件的方法。 优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。 至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。 在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

公开(公告)号：US20080194087A1

公开(公告)日：2008-08-14

申请号：US11729009

申请日：2007-03-28

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L21/3205 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L29/7834 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

公开(公告)号：US20080194072A1

公开(公告)日：2008-08-14

申请号：US11705655

申请日：2007-02-12

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

公开(公告)号：US20080191352A1

公开(公告)日：2008-08-14

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US20120094464A1

公开(公告)日：2012-04-19

申请号：US13336887

申请日：2011-12-23

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

IPC分类号： H01L21/762

CPC分类号： H01L21/76202 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

摘要翻译： 包括可折入隔离结构的半导体器件和用于制造这种器件的方法。 优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。 至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。 在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

公开(公告)号：US07892909B2

公开(公告)日：2011-02-22

申请号：US11729009

申请日：2007-03-28

申请人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Ding-Yuan Chen ,  Chu-Yun Fu ,  Liang-Gi Yao ,  Chen-Nan Yeh

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

公开(公告)号：US07880303B2

公开(公告)日：2011-02-01

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US07629655B2

公开(公告)日：2009-12-08

申请号：US11688592

申请日：2007-03-20

申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

IPC分类号： H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653

摘要： A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

摘要翻译： 提供了一种用于形成具有降低的源极/漏极延伸寄生电阻的半导体器件的系统和方法。 一个实施例包括在形成硅化物接触之后，将两种金属（例如用于NMOS晶体管的镱和镍或用于PMOS晶体管的铂和镍）注入到源极/漏极延伸部中。 然后进行退火以在源极/漏极延伸部内产生第二硅化物区域。 任选地，可以在第二硅化物区域上进行第二退火以迫使进一步的反应。 该过程可以对同一衬底上的多个半导体器件执行。

公开(公告)号：US20080303104A1

公开(公告)日：2008-12-11

申请号：US11758043

申请日：2007-06-05

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

IPC分类号： H01L29/94

CPC分类号： H01L21/76202 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

摘要翻译： 包括可折入隔离结构的半导体器件和用于制造这种器件的方法。 优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。 至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。 在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。