公开(公告)号：US6110785A

公开(公告)日：2000-08-29

申请号：US69533

申请日：1998-04-29

申请人： Thomas E. Spikes, Jr. ,  Mark I. Gardner ,  Anthony J. Toprac

发明人： Thomas E. Spikes, Jr. ,  Mark I. Gardner ,  Anthony J. Toprac

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L29/7833

摘要： The present invention is directed to a new and improved technique for formation of metal oxide semiconductor field effect transistors. In particular, the method involves formation of an initial gate structure that is wider than the desired final channel length of the completed transistor. Thereafter, an initial heavy-doping step is applied to the drain and source regions of the device. The width of the gate structure is then patterned and etched back to the desired final channel length of the device. A second, light-doping LDD implant is performed to complete the source and drain regions of the finished device.

摘要翻译： 本发明涉及用于形成金属氧化物半导体场效应晶体管的新的和改进的技术。 特别地，该方法涉及形成比完成的晶体管的期望的最终沟道长度更宽的初始栅极结构。 此后，将初始的重掺杂步骤施加到器件的漏极和源极区域。 然后将栅极结构的宽度图案化并蚀刻回设备的期望的最终通道长度。 执行第二个光掺杂LDD注入以完成成品器件的源极和漏极区域。

公开(公告)号：US06706541B1

公开(公告)日：2004-03-16

申请号：US09421803

申请日：1999-10-20

申请人： Anthony J. Toprac ,  Michael L. Miller

发明人： Anthony J. Toprac ,  Michael L. Miller

IPC分类号： H01L2100

CPC分类号： H01J37/32935 ,  H01J37/3299

摘要： A processing system includes a sensor, a processing tool, and an automatic process controller. The sensor has a plurality of sensing regions. The processing tool is adapted to process at least one process layer on a wafer. The process tool includes a process control device controllable by a process control variable. The sensor is adapted to measure a process layer characteristic of the process layer in a selected one of the sensing regions. The automatic process controller is adapted to receive the process layer characteristics measured by the sensor and adjust the process control variable in response to the process layer characteristic measured in one sensing region differing from the process layer characteristic measured in another sensing region. A method for controlling wafer uniformity includes processing a process layer on a wafer; measuring a characteristic of the layer in a plurality of sensing locations; and changing a process control variable of a process control device in response to the process layer characteristic measured in one sensing location differing from the process layer characteristic measured in another sensing location to affect the rate of processing the process layer in at least one of the sensing locations.

摘要翻译： 处理系统包括传感器，处理工具和自动过程控制器。 传感器具有多个感测区域。 处理工具适于处理晶片上的至少一个处理层。 处理工具包括可由过程控制变量控制的过程控制装置。 传感器适于测量所选感测区域中的处理层的处理层特性。 自动过程控制器适于接收由传感器测量的过程层特性，并且响应于在与另一感测区域中测量的处理层特性不同的一个感测区域中测量的过程层特性来调整过程控制变量。 一种用于控制晶片均匀性的方法包括处理晶片上的处理层; 测量多个感测位置中的层的特性; 以及响应于在一个感测位置中测量的处理层特性改变过程控制设备的过程控制变量，所述过程控制变量与在另一感测位置中测量的过程层特性不同，以影响在至少一个感测中处理过程层的速率 位置。

公开(公告)号：US06532428B1

公开(公告)日：2003-03-11

申请号：US09414190

申请日：1999-10-07

申请人： Anthony J. Toprac

发明人： Anthony J. Toprac

IPC分类号： G01B1100

CPC分类号： H01L21/67253 ,  H01L22/20

摘要： The present invention provides for a method and an apparatus for performing automatic calibration of a critical dimension metrology. A process run of semiconductor devices is performed. Critical dimension measurements are performed upon at least one the processed semiconductor device. A calibration adjustment procedure is performed using the critical dimension measurements.

摘要翻译： 本发明提供了一种用于执行关键尺寸度量的自动校准的方法和装置。 执行半导体器件的工艺流程。 至少一个处理的半导体器件执行临界尺寸测量。 使用临界尺寸测量执行校准调整程序。

公开(公告)号：US06460002B1

公开(公告)日：2002-10-01

申请号：US09501494

申请日：2000-02-09

申请人： Christopher A. Bone ,  Anthony J. Toprac

发明人： Christopher A. Bone ,  Anthony J. Toprac

IPC分类号： G06F1900

CPC分类号： G05B19/41865 ,  G05B2219/32053 ,  G05B2219/37532 ,  G05B2219/45031 ,  H01L21/67276 ,  Y02P90/20

摘要： In one embodiment, a method and apparatus is provided for data stackification for run-to-run control. A process run of semiconductor devices is processed. A manufacturing tag associated with the process run of semiconductor devices is recorded. Metrology data relating to the processed semiconductor devices is then acquired. The present invention calls for performing a metrology data stackification process upon the metrology data using the manufacturing tag for organizing and stacking the metrology data. The present invention provides for modifying at least one control parameter based upon the stacked metrology data.

摘要翻译： 在一个实施例中，提供了用于运行到运行控制的数据叠加的方法和装置。 处理半导体器件的工艺流程。 记录与半导体器件的工艺流程相关联的制造标签。 然后获取与处理的半导体器件有关的计量数据。 本发明要求使用制造标签对计量数据执行计量数据叠加处理，以用于组织和堆叠度量数据。 本发明提供了基于堆叠的度量数据来修改至少一个控制参数。

公开(公告)号：US06442496B1

公开(公告)日：2002-08-27

申请号：US09633930

申请日：2000-08-08

申请人： Alexander J. Pasadyn ,  Anthony J. Toprac

发明人： Alexander J. Pasadyn ,  Anthony J. Toprac

IPC分类号： H01L2100

CPC分类号： H01L21/67276 ,  H01L22/20

摘要： The present invention provides for a method and an apparatus for performing dynamic sampling of a production line. A first plurality of semiconductor wafers are processed. A minimum sampling rate of semiconductor wafers is calculated. Wafers from the first plurality of the semiconductor wafers are selected and analyzed at the calculated sampling rate. The performance of the processing of the first plurality of semiconductor wafers is quantified, based upon the analyzed wafers. A dynamic sampling process is performed based upon the quantification of the performance of the processing of semiconductor wafers.

摘要翻译： 本发明提供一种用于进行生产线的动态取样的方法和装置。 处理第一多个半导体晶片。 计算半导体晶片的最小采样率。 以所计算的采样率选择和分析来自第一多个半导体晶片的晶片。 基于分析的晶片来量化第一多个半导体晶片的处理性能。 基于对半导体晶片的处理的性能的量化来执行动态采样处理。

公开(公告)号：US06387823B1

公开(公告)日：2002-05-14

申请号：US09577756

申请日：2000-05-23

申请人： Thomas Sonderman ,  Anthony J. Toprac

发明人： Thomas Sonderman ,  Anthony J. Toprac

IPC分类号： C13C1600

CPC分类号： H01L21/67253

摘要： A method for controlling a deposition process, includes providing a wafer in a chamber of a deposition tool, the deposition tool being adapted to operate in accordance with a recipe; providing reactant gases to the chamber, the reactant gases reacting to form a layer on the wafer; allowing exhaust gases to exit the chamber; measuring characteristics of exhaust gases; and changing the recipe based on the characteristics of the exhaust gases. A deposition tool includes a chamber, a gas supply line, a gas exhaust line, a gas analyzer, and a controller. The chamber is adapted to receive a wafer. The gas supply line is coupled to the chamber for providing reactive gases. The gas exhaust line is coupled to the chamber for receiving exhaust gases. The gas analyzer is coupled to the gas exhaust line and adapted to determine characteristics of the exhaust gases. The controller is adapted to control the processing of the wafer in the chamber based on the characteristics of the exhaust gases.

摘要翻译： 一种用于控制沉积过程的方法，包括在沉积工具的腔室中提供晶片，所述沉积工具适于根据配方进行操作; 向所述室提供反应气体，所述反应气体反应以在所述晶片上形成层; 允许废气离开室; 测量排气特性; 并根据废气特性改变配方。 沉积工具包括室，气体供应管线，排气管线，气体分析器和控制器。 腔室适于接收晶片。 气体供应管线连接到室以提供反应性气体。 排气管线连接到用于接收废气的室。 气体分析器耦合到排气管线并且适于确定废气的特性。 控制器适于基于排气的特性来控制室中的晶片的处理。

公开(公告)号：US06379980B1

公开(公告)日：2002-04-30

申请号：US09625587

申请日：2000-07-26

申请人： Anthony J. Toprac

发明人： Anthony J. Toprac

IPC分类号： H01L2100

CPC分类号： H01L21/67253 ,  H01L21/67069 ,  H01L22/26

摘要： A method for monitoring the performance of a material removal tool includes providing a wafer having at least one process layer formed thereon; measuring the thickness of the process layer; removing at least a portion of the process layer in the material removal tool until an endpoint of the removal process is reached; determining a removal rate based on the measured thickness of the process layer and a duration of the removal process until the endpoint is reached; and comparing the determined removal rate to an expected removal rate to monitor the performance of the material removal tool. A processing line includes a metrology tool, a material removal tool, and a process controller. The metrology tool is adapted to measure a thickness of a process layer formed on a wafer. The material removal tool is adapted to remove at least a portion of the process layer until an endpoint is reached. The process controller is adapted to determine a removal rate based on the measured thickness of the process layer and a duration of the removal process until the endpoint is reached and compare the determined removal rate to an expected removal rate to monitor the performance of the material removal tool.

摘要翻译： 一种用于监测材料去除工具的性能的方法包括提供其上形成有至少一个工艺层的晶片; 测量工艺层的厚度; 去除所述材料去除工具中的所述工艺层的至少一部分，直到达到所述去除工艺的端点; 基于所测量的处理层的厚度和去除过程的持续时间确定去除速率直到达到端点; 并将确定的去除速率与预期去除速率进行比较以监测材料去除工具的性能。 处理线包括计量工具，材料去除工具和过程控制器。 测量工具适于测量在晶片上形成的工艺层的厚度。 材料去除工具适于去除工艺层的至少一部分，直到达到端点。 过程控制器适于基于所测量的处理层的厚度和去除过程的持续时间来确定去除速率，直到达到端点，并将确定的去除速率与预期去除速率进行比较以监测材料去除的性能 工具。

公开(公告)号：US6133132A

公开(公告)日：2000-10-17

申请号：US488605

申请日：2000-01-20

申请人： Anthony J. Toprac ,  John R. Behnke ,  Matthew Purdy

发明人： Anthony J. Toprac ,  John R. Behnke ,  Matthew Purdy

IPC分类号： H01L21/336 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66575 ,  H01L22/20 ,  H01L29/6659

摘要： A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer. The automatic process controller is adapted to determine a portion of the insulative layer to be removed based on the measured thickness of the insulative layer. The spacer etch tool is adapted to remove the portion of the insulative layer to define a spacer on the gate.

摘要翻译： 提供了一种用于控制半导体器件中的间隔物宽度的方法。 提供其上形成有栅极的基板。 在衬底的至少一部分上形成绝缘层。 绝缘层覆盖门。 测量绝缘层的厚度。 基于所测量的绝缘层的厚度来确定要去除的绝缘层的一部分。 去除绝缘层的部分以在栅极上限定间隔物。 用于在设置在基板上的栅极上形成间隔物的处理线包括沉积工具，厚度计量工具和自动过程控制器以及间隔物蚀刻工具。 沉积工具适于在衬底的至少一部分上形成绝缘层。 绝缘层覆盖门。 厚度测量工具适用于测量绝缘层的厚度。 自动处理控制器适于基于所测量的绝缘层的厚度来确定要去除的绝缘层的一部分。 间隔蚀刻工具适于去除绝缘层的部分以在栅极上限定间隔物。

公开(公告)号：US06746958B1

公开(公告)日：2004-06-08

申请号：US09817536

申请日：2001-03-26

申请人： Joyce S. Oey Hewett ,  Gerd Franz Christian Marxsen ,  Anthony J. Toprac

发明人： Joyce S. Oey Hewett ,  Gerd Franz Christian Marxsen ,  Anthony J. Toprac

IPC分类号： H01L214763

CPC分类号： B24B37/013 ,  B24B37/042 ,  H01L21/7684

摘要： The present invention is directed to a method of controlling chemical mechanical polishing operations to control the duration of an endpoint polishing process. The method comprises providing a wafer having a layer of copper formed thereabove, performing a first timed polishing operation for a duration (t1) on the layer of copper at a first platen to remove a majority of the layer of copper, performing an endpoint polishing operation on the layer of copper at a second platen to remove substantially all of the layer of copper, determining a duration (t2ept) of the endpoint polishing operation performed on the layer of copper at the second platen, and determining, based upon a comparison between the determined duration (t2ept) of the endpoint polishing operation and a target value for the duration of the endpoint polishing operations, a duration (t1) of the timed polishing operation to be performed on a subsequently processed layer of copper at the first platen. In another embodiment, the invention further comprises modifying, based upon a variance between the determined duration (t2ept) of the endpoint polishing operation and a target value for the duration (t2ept) of the endpoint polishing operation, the duration (t1) of the timed polishing operation to be performed on a subsequently processed layer of copper at the first platen.

摘要翻译： 本发明涉及一种控制化学机械抛光操作以控制端点抛光工艺的持续时间的方法。 该方法包括提供具有形成在其上的铜层的晶片，在第一压板上在铜层上执行持续时间（t1）的第一定时抛光操作以去除大部分铜层，执行端点抛光操作 在第二压板上的铜层上去除基本上所有的铜层，确定在第二压板上对铜层执行的端点抛光操作的持续时间（t2 ），并且基于 在终点抛光操作的确定的持续时间（t2 ）与终点抛光操作的持续时间的目标值之间进行比较，对后续处理的铜层执行的定时抛光操作的持续时间（t1） 第一个压板。 在另一个实施例中，本发明还包括基于端点抛光操作的所确定的持续时间（t2 ）与端点抛光操作的持续时间（t2 ）的目标值之间的差异来修改，持续时间 （t1）对在第一压板上的后续处理的铜层进行的定时抛光操作。

公开(公告)号：US06741903B1

公开(公告)日：2004-05-25

申请号：US09585199

申请日：2000-06-01

申请人： Christopher Allen Bode ,  Anthony J. Toprac

发明人： Christopher Allen Bode ,  Anthony J. Toprac

IPC分类号： G06F1900

CPC分类号： G05B19/41875 ,  B24B37/005 ,  G05B2219/32182 ,  Y02P90/22

摘要： A method is provided, the method comprising processing a workpiece, having a photolithography overlay target structure disposed thereon, using a chemical-mechanical planarization (CMP) tool and measuring a photolithography overlay parameter using the photolithography overlay target structure. The method also comprises forming an output signal corresponding to the photolithography overlay parameter measured and to the chemical-mechanical planarization (CMP) tool used and using the output signal to improve at least one of accuracy in photolithography overlay metrology and fault detection in chemical-mechanical planarization (CMP).

摘要翻译： 提供了一种方法，该方法包括使用化学机械平面化（CMP）工具处理其上设置有光刻覆盖目标结构的工件，并使用光刻覆盖目标结构测量光刻覆盖参数。 该方法还包括形成对应于所测量的光刻覆盖参数的对应的输出信号和使用的化学 - 机械平面化（CMP）工具，并使用输出信号来提高化学机械中的光刻重叠测量和故障检测的精度中的至少一个 平面化（CMP）。