公开(公告)号：US06660621B1

公开(公告)日：2003-12-09

申请号：US10163461

申请日：2002-06-07

申请人： Paul R. Besser ,  Minh Van Ngo

发明人： Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L213205

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/665

摘要： A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.

摘要翻译： 在半导体晶片中形成超浅结的方法形成栅极和源极/漏极结，其在栅极和源极/漏极结上的第一金属硅化物区具有上表面。 这些第一金属硅化物区域具有较高的电阻率。 通过等离子体增强化学气相沉积（PECVD）将非晶硅沉积在第一金属硅化物区域上。 PECVD工艺可以是较低压力的沉积工艺，在多个工位上执行以在多层中形成非晶硅层。 这就形成了跨越晶片的更均匀的非晶硅层和不同的图案化密度，从而提高了器件性能和特性。 然后通过第一金属硅化物区域和通过PECVD工艺沉积的非晶硅的扩散反应，进行退火以形成较低电阻率的第二金属硅化物区域。

公开(公告)号：US06492258B1

公开(公告)日：2002-12-10

申请号：US09881831

申请日：2001-06-14

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L214763

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，形成不希望的空隙的可能性。 在互连线路中减少。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。 并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

公开(公告)号：US06221794B1

公开(公告)日：2001-04-24

申请号：US09208596

申请日：1998-12-08

申请人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo

发明人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2131

CPC分类号： H01L21/3145 ,  C23C16/308 ,  H01L21/0276 ,  H01L21/76834 ,  H01L21/76885

摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During processing the deposition temperature is reduced to under 400 degrees Celsius, specifically temperatures in the range of about 350 degrees Celsius to about 380 degrees, Celsius, resulting in a substantially reduced incidence of stress-induced voiding in the underlying interconnect lines. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.

摘要翻译： 在基板的微电路互连线上形成层间电介质（ILD）涂层的方法中，通过使用等离子体增强化学气相沉积形成SiON层。 使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。 等离子体反应形成沉积在半导体衬底上的SiON。 在加工过程中，沉积温度降低至400摄氏度以下，特别是约350摄氏度至约380摄氏度的温度，导致底层互连线中应力引起的空隙的发生率基本上降低。 此外，在沉积期间，对沉积温度和工艺压力进行微调，以控制SiON层的光学特性。 测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。 一旦形成了ILD，底物就可以进行进一步的处理。

公开(公告)号：US06566252B1

公开(公告)日：2003-05-20

申请号：US09689144

申请日：2000-10-11

申请人： Paul R. Besser ,  Minh Van Ngo

发明人： Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2144

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801

摘要： A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

摘要翻译： 制造0.25微米半导体芯片的方法包括使用TEOS作为高密度等离子体（HDP）层间电介质（ILD）。 更具体地说，在基板上建立预定的铝线图案之后，TEOS沉积并与TEOS沉积同时被蚀刻掉，从而避免了铝线中的氢脆化和随后的空隙形成，否则如果硅烷是 用作HDP ILD。

公开(公告)号：US06534869B2

公开(公告)日：2003-03-18

申请号：US09128057

申请日：1998-07-29

申请人： Bryan Tracy ,  Paul R. Besser ,  Minh Van Ngo

发明人： Bryan Tracy ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2352

CPC分类号： H01L21/76858 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.

摘要翻译： 制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火过程中，首先形成铝和钛的合金，其随后体积收缩，由此形成铝化铝化合物，其中收缩被铝吸收。 因为在ILD沉积之前合金反应形成金属化合物，所以当它尝试吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。

公开(公告)号：US06225216B1

公开(公告)日：2001-05-01

申请号：US09418490

申请日：1999-10-15

申请人： Minh Van Ngo ,  Yowjuang Bill Liu ,  Paul R. Besser

发明人： Minh Van Ngo ,  Yowjuang Bill Liu ,  Paul R. Besser

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/3185 ,  H01L21/76895

摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased density in comparison to conventionally deposited (e.g., plasma enhanced chemical vapor deposition (PECVD) etch stop layers. A low pressure chemical vapor deposition (LPCVD) process is used to deposit LPCVD SiN, using a high temperature in the deposition chamber. The increased temperature during deposition creates a highly dense, thermal SiN etch stop layer that is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

摘要翻译： 与常规沉积（例如，等离子体增强化学气相沉积（PECVD）蚀刻停止层（例如，等离子体增强化学气相沉积（PECVD））蚀刻停止层相比，用于形成局部互连而不削弱场边缘或在场边缘处断开扩散区域的方法和装置提供了具有增加的密度 使用低压化学气相沉积（LPCVD）工艺来沉积LPCVD SiN，使用沉积室中的高温，沉积过程中增加的温度产生高度致密的热SiN蚀刻停止层，其比常规PECVD蚀刻更慢 SiON，使得当蚀刻其中随后沉积局部互连材料的电介质层时，蚀刻以受控的方式停止在蚀刻停止层处，这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

公开(公告)号：US07049666B1

公开(公告)日：2006-05-23

申请号：US10859286

申请日：2004-06-01

申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L29/94 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成一个薄的绝缘层。 在薄绝缘层和栅极上形成硅化物。 在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

公开(公告)号：US06602754B1

公开(公告)日：2003-08-05

申请号：US10059039

申请日：2002-01-30

申请人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

发明人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/265

摘要： Bridging between silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by implanting the exposed surfaces of the silicon nitride sidewall spacers with nitrogen to create a surface region having an increased nitrogen concentration. Embodiments include implanting the silicon nitride sidewall spacers with nitrogen such that the nitrogen concentration of the exposed surface is increased by about 5% to about 15%, thereby substantially preventing the formation of metal silicide on the sidewall spacers.

摘要翻译： 通过用氮气注入氮化硅侧壁间隔物的暴露表面以产生具有增加的氮浓度的表面区域来防止在栅电极上的硅化物层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮气注入氮化硅侧壁间隔物，使得暴露表面的氮浓度增加约5％至约15％，从而基本上防止在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06432805B1

公开(公告)日：2002-08-13

申请号：US09783620

申请日：2001-02-15

申请人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

发明人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.

摘要翻译： 通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理 桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

公开(公告)号：US06171919B2

公开(公告)日：2001-01-09

申请号：US09361155

申请日：1999-07-27

申请人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

发明人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施例包括通过进行氢离子等离子体处理来除去碳质残渣。