公开(公告)号：US06329718B1

公开(公告)日：2001-12-11

申请号：US09105775

申请日：1998-06-26

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性 在ILD形成期间。

公开(公告)号：US06492258B1

公开(公告)日：2002-12-10

申请号：US09881831

申请日：2001-06-14

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L214763

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，形成不希望的空隙的可能性。 在互连线路中减少。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。 并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

公开(公告)号：US06809402B1

公开(公告)日：2004-10-26

申请号：US10217403

申请日：2002-08-14

申请人： Dawn Hopper ,  Minh Van Ngo ,  Atul Gupta ,  Tyagamohan Gottipati ,  John Caffall

发明人： Dawn Hopper ,  Minh Van Ngo ,  Atul Gupta ,  Tyagamohan Gottipati ,  John Caffall

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L27/115

摘要： Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.

摘要翻译： 通过沉积能够流入底切区域的B掺杂的HDP或掺有BP的HDP氧化物间隙填充层来补救由间隔物底切造成的器件泄漏。 实施例包括沉积含有4至6重量％的B或BP掺杂的HDP氧化物膜。 ％B超过紧密间隔开的非挥发性晶体管，并且在沉积期间和之后加热，以使B-或BP-HDP氧化物完全流入并填充侧壁间隔物上的底切区域并致密化B或BP-HDP氧化物 。

公开(公告)号：US6060404A

公开(公告)日：2000-05-09

申请号：US924130

申请日：1997-09-05

申请人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

发明人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

IPC分类号： H01L21/314 ,  H01L21/768 ,  H01L21/72

CPC分类号： H01L21/76801 ,  H01L21/3144 ,  H01L21/76834 ,  H01L21/76895

摘要： An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.

摘要翻译： 原位沉积方法允许形成适合用于在半导体晶片中形成导电路径的电介质层。 该方法包括在具有低压的化学气相沉积（CVD）反应器室内的半导体晶片的顶部上沉积薄的SiOxNy阻挡层，保持在沉积SiO x N y终止层之后的低压，然后沉积厚的TEOS氧化物 在CVD反应器室内的SiOxNy停止层上的介电层。 原位沉积过程减少了通常在SiON阻挡层和TEOS氧化物介电层之间的界面处形成的除气缺陷。

公开(公告)号：US07118967B1

公开(公告)日：2006-10-10

申请号：US10368696

申请日：2003-02-19

申请人： Minh V. Ngo ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Cyrus Tabery ,  John Caffall ,  Tyagamohan Gottipati ,  Dawn Hopper

发明人： Minh V. Ngo ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Cyrus Tabery ,  John Caffall ,  Tyagamohan Gottipati ,  Dawn Hopper

IPC分类号： H01L21/336

CPC分类号： H01L29/7923 ,  H01L29/66833 ,  Y10S438/954

摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.

摘要翻译： 一种保护电荷捕获电介质闪存单元免受UV感应充电的方法，包括在半导体器件中制造包括电荷捕获介电电荷存储层的电荷捕获电介质闪存单元; 并且在形成电荷捕获介电电荷存储层之后的处理步骤期间，保护电荷捕获电介质闪速存储器单元暴露于足以在电荷俘获电介质闪存单元中沉积不可擦除电荷的UV辐射水平。 在一个实施例中，保护步骤是通过选择不包括半导体器件的使用，产生或曝光到足以沉积不可擦除电荷的紫外线辐射的水平的BEOL制造中的工艺进行的。