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    Co-deposition of nitrogen and metal for metal silicide formation
    1.
    发明授权
    Co-deposition of nitrogen and metal for metal silicide formation 有权
    用于金属硅化物形成的氮和金属的共沉积

    公开(公告)号：US06432805B1

    公开(公告)日：2002-08-13

    申请号：US09783620

    申请日：2001-02-15

    申请人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

    发明人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

    摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.

    摘要翻译： 通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理 桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

    Shallow trench isolation process
    5.
    发明授权
    Shallow trench isolation process 有权
    浅沟槽隔离工艺

    公开(公告)号：US07648886B2

    公开(公告)日：2010-01-19

    申请号：US10341863

    申请日：2003-01-14

    申请人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

    发明人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

    摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫形成为能够减少锗除气的低温过程。 低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

    Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
    10.
    发明授权
    Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
    用于嵌入栅极MOS晶体管的介电材料前体材料的无电沉积

    公开(公告)号：US06559051B1

    公开(公告)日：2003-05-06

    申请号：US09679881

    申请日：2000-10-05

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

    IPC分类号： H01L2144

    CPC分类号： H01L21/28194 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66583

    摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

    摘要翻译： 通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层 金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应 的半导体衬底以形成至少一种金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。