公开(公告)号：US06998694B2

公开(公告)日：2006-02-14

申请号：US10633500

申请日：2003-08-05

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L27/095

CPC classification number: H01L29/8725 ,  H01L29/0623 ,  H01L29/66143 ,  H01L29/872

Abstract: A power Schottky rectifier device and its fabrication method are disclosed. The method comprises the following steps: First, a semiconductor substrate having a relatively heavily doped n+ doped layer and a lightly doped is provided. A buried p region is then formed in the epi layer by ion implantation. Afterward, a first oxide layer and a nitride layer are then successively formed on the epi layer. The result structure is then patterned to form trenches. Subsequently, a thermal oxidation step is performed to recover etch damage. A wet etch is then performed to remove the thin oxide layer in the trench to expose the silicon in the sidewall. After that, a silicidation process is then performed to form silicide layer on the n-epi-layer in the trenches. After a removal of un-reacted metal layer, a top metal layer is then formed on the silicide layer and on the first oxide layer or nitride layer. The top metal layer on the termination region portion is then patterned to define anode. Finally, after backside layers formed on the rear surface of the substrate are removed, another cathode layer is formed on the rear surface.

Abstract translation: 公开了一种功率肖特基整流器及其制造方法。 该方法包括以下步骤：首先，提供具有相对重掺杂的n +掺杂层和轻掺杂的半导体衬底。 然后通过离子注入在外延层中形成掩埋的p区。 之后，在epi层上依次形成第一氧化物层和氮化物层。 然后将结果结构图案化以形成沟槽。 随后，进行热氧化步骤以恢复蚀刻损伤。 然后进行湿蚀刻以去除沟槽中的薄氧化物层以露出侧壁中的硅。 之后，然后进行硅化处理以在沟槽中的n外延层上形成硅化物层。 在去除未反应的金属层之后，在硅化物层和第一氧化物层或氮化物层上形成顶部金属层。 然后将终止区域部分上的顶部金属层图案化以限定阳极。 最后，在衬底的后表面上形成的背面层被去除之后，在后表面上形成另一个阴极层。

公开(公告)号：US06825073B1

公开(公告)日：2004-11-30

申请号：US10663666

申请日：2003-09-17

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21338

CPC classification number: H01L29/66143 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/872

Abstract: A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide layer is form on the epi layer. A patterning step to pattern first oxide layer and recess the epi layer (optional) is then followed to define guard rings. After stripping the photoresist pattern, a polycrystalline silicon layer formation is then followed. A boron and/or BF2+ ion implant is then performed. Subsequently, a high temperature drive in process and oxidation process to oxidize the polycrystalline silicon layer and drive ions is then carried out. A second mask and etch steps are then performed to open the active regions. A metallization process is then done. A third mask and etch steps are then implemented to define anode. Finally, a backside metal layer is then formed and serves as a cathode.

Abstract translation: 公开了一种肖特基二极管结构及其制造方法。 该方法包括以下步骤：首先，提供具有掺杂有相同类型杂质的第一导电层和外延层的半导体衬底。 然后在epi层上形成第一氧化物层。 然后遵循图案化第一氧化物层和凹陷外延层（可选）的图案化步骤以限定保护环。 在剥离光致抗蚀剂图案之后，然后遵循多晶硅层形成。 然后进行硼和/或BF 2+离子注入。 随后，进行用于氧化多晶硅层并驱动离子的工艺和氧化工艺中的高温驱动。 然后执行第二掩模和蚀刻步骤以打开活性区域。 然后进行金属化处理。 然后实施第三掩模和蚀刻步骤以定义阳极。 最后，形成背面金属层，并用作阴极。

公开(公告)号：US06358818B1

公开(公告)日：2002-03-19

申请号：US09361447

申请日：1999-07-26

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21762

CPC classification number: H01L21/76202

Abstract: The method for forming an isolation region in the present invention mainly includes the following steps. First, a pad layer is formed on a semiconductor substrate and an oxidation masking layer is formed on the pad layer. The oxidation masking layer, the pad layer, and the substrate are then patterned to form trenches in the substrate. The pad layer is removed laterally to form undercut structures under the oxidation masking layer. A doped layer is conformably formed on the oxidation masking layer, the undercut structures of the pad layer, and the substrate in the trenches. Next, a thermally oxidizing step is carried out to oxidize the doped layer to form an oxidized layer conformably on the oxidation masking layer, the undercut structures of the pad layer, and the substrate in the trenchs. A dielectric layer is formed over the substrate to fill up the trenches and cover over the pad layer and the oxidation masking layer. The dielectric layer is planarized downward to portions of the oxidation masking layer. Finally, the oxidation masking layer and the pad layer are removed.

Abstract translation: 本发明中形成隔离区域的方法主要包括以下步骤。 首先，在半导体基板上形成焊盘层，在焊盘层上形成氧化掩模层。 然后将氧化掩蔽层，焊盘层和衬底图案化以在衬底中形成沟槽。 衬垫层被横向移除以在氧化掩蔽层下形成底切结构。 掺杂层顺应地形成在氧化屏蔽层上，衬垫层的底切结构和沟槽中的衬底。 接下来，进行热氧化步骤以氧化掺杂层以在氧化屏蔽层，衬垫层的底切结构和沟槽中的衬底上形成氧化层。 在衬底上方形成介电层以填充沟槽并覆盖衬垫层和氧化屏蔽层。 介电层向下平面化到氧化掩模层的部分。 最后，去除氧化屏蔽层和焊盘层。

公开(公告)号：US06323094B1

公开(公告)日：2001-11-27

申请号：US09345925

申请日：1999-07-01

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/518

Abstract: The method of the present invention is to fabricate a CMOS device without boron penetration. A nitrided gate oxide and SAS gate electrode are provided to suppress boron penetration. The nitrided gate oxide could be formed in two approaches. One of the approaches is to implant nitrogen ions into the interface between substrate and pad oxide layer, and then thermally treat the substrate for segregating the doped nitrogen ions in the surface of substrate. Removing the pad oxide layer, thermally treating the substrate in oxygen ambient for growing a gate oxide layer, the nitrided gate oxide layer is formed by incorporating doped nitrogen ions into the growing gate oxide layer. The other approach is to place the substrate having a gate oxide layer thereon in nitrogen plasma ambient, thereby forming the nitrided gate oxide layer. After the formation of nitrided gate oxide layer, at least one stacked amorphous silicon (SAS) layer is formed over the gate oxide layer. The gate structure is formed by patterning the SAS layer and nitrided gate oxide layer. Thereafter, source/drain with LDD regions are subsequently formed in the substrate. Finally, a thermal treatment is performed to convert the stacked-amorphous silicon gate into poly silicon gate and to form shallow source and drain junction in the substrate, thereby achieving the structure of the MOS device.

Abstract translation: 本发明的方法是制造没有硼渗透的CMOS器件。 提供氮化栅极氧化物和SAS栅电极以抑制硼渗透。 氮化栅氧化物可以以两种方式形成。 其中一种方法是将氮离子注入衬底和衬垫氧化物层之间的界面，然后热处理衬底以分离衬底表面中的掺杂氮离子。 通过去除衬垫氧化物层，在氧环境中热处理衬底以生长栅极氧化物层，氮化栅极氧化物层通过将掺杂的氮离子掺入到生长栅极氧化物层中而形成。 另一种方法是将其上具有栅氧化层的衬底放置在氮等离子体环境中，从而形成氮化栅极氧化物层。 在形成氮化栅极氧化物层之后，在栅极氧化物层上形成至少一个层叠的非晶硅（SAS）层。 栅极结构通过图案化SAS层和氮化栅极氧化物层而形成。 此后，随后在衬底中形成具有LDD区的源极/漏极。 最后，进行热处理，将层叠的非晶硅栅极转换为多晶硅栅极，并在衬底中形成浅的源极和漏极结，从而实现MOS器件的结构。

公开(公告)号：US06316316B1

公开(公告)日：2001-11-13

申请号：US09336870

申请日：1999-06-18

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21336

CPC classification number: H01L28/82 ,  H01L29/66825

Abstract: The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. A portion of the first nitride layer and of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and the first oxide layer is removed to expose a portion of the substrate under the first oxide layer. Silicon grains are formed on the pad oxide layer, the exposed portion of substrate, and the second oxide layer. The exposed portion of the substrate is then etched to leave a rugged surface on the exposed portion of the substrate. A second thermal process is performed to form a tunnel oxide layer on the rugged surface. A first conductive layer is formed over the substrate and a portion of the first conductive layer is removed to define a floating gate. A dielectric layer is formed over the semiconductor substrate and a second conductive layer is then formed over as a control gate.

Abstract translation: 用于形成闪速存储器的方法包括以下步骤。 首先，提供形成有隔离区域的半导体衬底。 半导体衬底具有衬垫氧化物层和形成在其上的第一氮化物层。 去除第一氮化物层和焊盘氧化物层的一部分以限定栅极区域。 形成第一氧化物层，然后形成侧壁结构。 半导体衬底掺杂有第一类型掺杂剂。 执行第一热处理以形成第二氧化物层并在第一类掺杂剂中驱动。 然后去除侧壁结构和第一氮化物层，并且去除第一氧化物层以暴露第一氧化物层下的衬底的一部分。 在衬垫氧化物层，衬底的暴露部分和第二氧化物层上形成硅晶粒。 然后蚀刻衬底的暴露部分以在衬底的暴露部分上留下粗糙的表面。 执行第二热处理以在凹凸的表面上形成隧道氧化物层。 第一导电层形成在衬底上，并且去除第一导电层的一部分以限定浮动栅极。 在半导体衬底之上形成电介质层，然后形成第二导电层作为控制栅极。

公开(公告)号：US06268245B1

公开(公告)日：2001-07-31

申请号：US09298927

申请日：1999-04-22

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218242

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L28/91

Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer. A fourth dielectric layer is formed on the first conductive layer and the substrate is planarized to the surface of the third dielectric layer. The fourth dielectric layer and the third dielectric layer are then removed to leave a storage node which is composed of the first conductive layer. Finally, a fifth dielectric layer is formed on the storage node, and a second conductive layer is then formed on the fifth dielectric layer to finish the capacitor structure.

Abstract translation: 在用于形成动态随机存取存储单元的粗糙多晶硅冠状电容器的优选实施例中，在半导体衬底上形成第一介电层。 去除第一电介质层的一部分以限定第一电介质层内的接触孔，其中接触孔向下延伸到衬底中的源极区域。 接下来，形成导电插塞并将其连通到接触孔内的源极区域。 在第一电介质层和导电插塞上形成第二电介质层，在第二电介质层上形成第三电介质层。 接下来，去除第三电介质层和第二电介质层的部分以限定存储节点开口，其中存储节点开口位于导电插塞上方。 然后形成第一导电层，以一致地覆盖存储节点开口的内表面和第三介电层。 在第一导电层上形成第四电介质层，并且将基板平面化到第三电介质层的表面。 然后去除第四电介质层和第三电介质层以留下由第一导电层构成的存储节点。 最后，在存储节点上形成第五电介质层，然后在第五电介质层上形成第二导电层以完成电容器结构。

公开(公告)号：US06251731B1

公开(公告)日：2001-06-26

申请号：US09351873

申请日：1999-07-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L218234

CPC classification number: H01L27/1126 ,  H01L21/823412

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines. A high temperature annealing is carried out to form polycide in the word line regions, thereby finishing the fabrication.

Abstract translation: 本发明提出了一种用于制造高密度和高速NAND型掩模只读存储器的方法。 该方法通过掺杂剂扩散到硅衬底中构成掺杂源和漏极以形成超浅结，从而最小化穿通问题。 首先，在半导体衬底上沉积堆叠的薄氧化物，掺杂硅和氮化硅层，然后定义位线区域。 栅极氧化膜形成在位线区域之间，并且硅层中的掺杂剂被驱动到衬底中以形成用于源极和漏极区域的浅结。 在衬底上沉积掺杂多晶硅层，并以氮化硅作为阻挡层进行化学机械抛光工艺。 执行编码注入，并且在多晶硅层上限定作为字线的导电层。 进行高温退火以在字线区域中形成多硅化物，从而完成制造。

公开(公告)号：US06207999B1

公开(公告)日：2001-03-27

申请号：US09238381

申请日：1999-01-27

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L2976

CPC classification number: H01L27/11253 ,  H01L27/11293

Abstract: The present invention provides a mask ROM memory to minimize band-to-band leakage. The substrate includes a normal NMOS device region and a NMOS cell region for coding. An isolation region is formed between the normal NMOS device region and the NMOS cell region. A gate oxide layer is formed on the normal NMOS device region and a coding oxide layer is formed on the NMOS cell region, respectively. In the preferred embodiments, the coding oxide layer has a thickness of about two to ten times that of the gate oxide layer. Main gates are respectively formed on the gate oxide layer and the coding oxide layer. In the present invention, the main gates comprise materials like metal and metal compounds. Spacers are formed on the side walls of the main gates. First doped regions of source and drain regions, or namely lightly doped drains (LDD) and sources, are formed under the spacers and are adjacent to the main gates. Second doped regions of the source and drain regions are formed next to and outside the first doped regions. The second doped regions have a heavier dose than the first doped regions. A p type doped region is formed under the coding oxide layer and adjacent to a surface of the NMOS cell region. The p type doped region is doped with dopants like aluminum-containing, gallium-containing, indium-containing, or thallium-containing dopants. The p type doped region has higher resistance than the other normal NMOS devices during the operation.

Abstract translation: 本发明提供一种掩模ROM存储器，以最小化频带到频带的泄漏。 衬底包括正常的NMOS器件区域和用于编码的NMOS单元区域。 在正常NMOS器件区域和NMOS单元区域之间形成隔离区域。 在正常NMOS器件区上形成栅氧化层，在NMOS单元区分别形成编码氧化层。 在优选实施例中，编码氧化物层的厚度为栅极氧化物层的厚度的约2至10倍。 主栅极分别形成在栅极氧化层和编码氧化物层上。 在本发明中，主栅极包括金属和金属化合物等材料。 隔板形成在主闸门的侧壁上。 源极和漏极区域的第一掺杂区域，即轻掺杂漏极（LDD）和源极，形成在间隔物下方并与主栅极相邻。 源极和漏极区域的第二掺杂区域形成在第一掺杂区域的旁边和外部。 第二掺杂区具有比第一掺杂区更重的剂量。 p型掺杂区形成在编码氧化层的下方并与NMOS单元区的表面相邻。 p型掺杂区域掺杂有诸如含铝，含镓，含铟或含铊掺杂剂的掺杂剂。 在操作期间，p型掺杂区域具有比其他正常的NMOS器件更高的电阻。

公开(公告)号：US06200861B1

公开(公告)日：2001-03-13

申请号：US09276646

申请日：1999-03-26

Applicant: Shye-Lin Wu ,  Ling Chen

Inventor： Shye-Lin Wu ,  Ling Chen

IPC: H01L218236

CPC classification number: H01L27/11246 ,  H01L27/112 ,  H01L27/1126

Abstract: A method of fabricating high density multiple states mask ROM cells on a semiconductor substrate is disclosed. The method comprises the following steps. Firstly, the array of buried bit line is formed on semiconductor substrate. Then, a CVD oxide film is deposited on said substrate. The first coding mask is applied to dip out the CVD oxide film on the uncoded regions. Then, a thin gate oxide film is thermally grown on said substrate. At the same time, the CVD oxide film is densified and the N+source/drain junction of buried bit lines is formed. A conductive layer is then deposited on all area followed by defining the word lines. The second coding process is performed by using a high energy boron ion implantation through the conductive layer and gate oxide film into said predetermined regions. By combination of the first CVD oxide coding process and the second boron ion implantation coding process, a high density mask ROM with a multiple states is fabricated.

Abstract translation: 公开了一种在半导体衬底上制造高密度多态掩模ROM单元的方法。 该方法包括以下步骤。 首先，在半导体衬底上形成掩埋位线阵列。 然后，CVD氧化膜沉积在所述衬底上。 应用第一编码掩模以在未编码区域上浸出CVD氧化物膜。 然后，在所述衬底上热生长薄栅氧化膜。 同时CVD氧化膜致密化，形成掩埋位线的N +源极/漏极结。 然后将导电层沉积在所有区域上，然后定义字线。 通过使用通过导电层和栅极氧化物膜的高能量硼离子注入到所述预定区域来执行第二编码处理。 通过第一CVD氧化物编码处理和第二硼离子注入编码处理的组合，制造具有多个状态的高密度掩模ROM。

公开(公告)号：US06180988B2

公开(公告)日：2001-01-30

申请号：US08984871

申请日：1997-12-04

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L2976

CPC classification number: H01L29/6659 ,  H01L21/2257 ,  H01L21/2652 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/7833 ,  Y10S257/90

Abstract: A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substrate and are separated with the gate by a space. Air gaps are formed between the gate and the spacers. First doped ion regions are formed aligned to the air gaps in the substrate, under a portion of the dielectric layer. Second doped ion regions are formed under the spacers in the substrate, next to the first doped ion regions. Third doped ion regions are formed in the substrate next to the second doped ion regions. The third doped ion regions have relatively highly doped ions to the first doped ion regions. The second doped ion regions are formed with immediately highly doped ions between the first and the third doped ion regions.

Abstract translation: MOSFET包括形成在衬底上的栅极氧化物。 在栅极的侧壁上形成薄的电介质层。 栅极形成在栅极氧化物上。 第一金属硅化物层形成在栅极的顶部以增加栅极的导电性。 隔板形成在基板上并与栅极分开一个空间。 在栅极和间隔物之间​​形成气隙。 在电介质层的一部分下方，将第一掺杂离子区域形成为与衬底中的气隙对准。 第二掺杂离子区域形成在衬底中的间隔物之下，紧邻第一掺杂离子区域。 第三掺杂离子区形成在第二掺杂离子区旁边的衬底中。 第三掺杂离子区域具有相对高掺杂的离子到第一掺杂离子区域。 第二掺杂离子区域在第一和第三掺杂离子区域之间立即形成高度掺杂的离子。