公开(公告)号：US06312989B1

公开(公告)日：2001-11-06

申请号：US09489496

申请日：2000-01-21

Applicant: Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

Inventor： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

Abstract translation: 公开了一种用于形成具有突出源的分裂栅极闪存单元来代替常规扁平源的方法。 垂直突出的源结构具有顶部和底部。 底部是多晶硅，而顶部是多晶氧化物。 源极上的突出结构的垂直壁用于形成具有中间栅极氧化物的垂直浮动栅极和间隔物控制栅极。 因为现在通过垂直壁提供源极和浮动栅极之间的耦合，所以耦合面积比常规扁平源大得多。 此外，不再存在源极和漏极之间的电压穿通的问题。 垂直浮动栅极也变薄，使得所得到的薄而尖锐的多尖端进一步增强了闪存单元的擦除和编程速度。 源结构和浮置栅极的垂直取向以及间隔物控制栅极与浮置栅极的自对准一起使得可以基本上减小存储单元。

公开(公告)号：US06251744B1

公开(公告)日：2001-06-26

申请号：US09356870

申请日：1999-07-19

Applicant: Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

Inventor： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC: H01L2176

CPC classification number: H01L21/76213

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract translation: 在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。 在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。 去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。 牺牲氧化物层沉积在半导体衬底的表面上。 在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

公开(公告)号：US06130168A

公开(公告)日：2000-10-10

申请号：US349844

申请日：1999-07-08

Applicant: Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

Inventor： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC: H01L21/32 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/302

CPC classification number: H01L27/11526 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/954

Abstract: A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.

Abstract translation: 描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。 提供半导体衬底，其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。 沉积在衬底表面上的隧道氧化物层上的多晶硅层。 去除多晶硅和隧道氧化物层，除了在存储单元区域中。 沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。 在高电压区域中去除ONO层。 衬底在高压区域被氧化以形成厚的栅极氧化物层。 此后，在低电压区域中去除ONO层，并且衬底被氧化以形成薄的栅极氧化物层。 第二多晶硅层沉积在存储区域中的ONO层上，在低电压区域的薄栅极氧化物层上方，以及高电压区域中的厚栅极氧化物层上方。 将存储单元区域中的第二多晶硅层，ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。 将第二多晶硅层图案化以在低电压区域中形成低压晶体管，并在高电压区域形成高压晶体管。

公开(公告)号：US6127229A

公开(公告)日：2000-10-03

申请号：US301222

申请日：1999-04-29

Applicant: Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

Inventor： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed. The polysilicon layer is then removed using the silicon oxide layer as an etch barrier, and the edge surfaces of the resulting polysilicon floating gates oxidized. A second polysilicon layer is deposited on the substrate and elongated word lines formed that are parallel and partially overlapping the floating gates. Source lines are formed in the substrate, and gate lines are formed that overlie the floating gates.

Abstract translation: 提出了一种用分裂栅极制造EEPROM器件的改进方法。 在该方法中，提供硅衬底，其具有间隔开且平行的凹陷氧化物区域，其隔离氧化物区域突出在衬底的顶表面上方的组分区域。 在衬底上形成薄栅氧化物，并且在栅极氧化物和突出的氧化物区域上沉积第一共形层。 然后将衬底进行化学机械抛光以去除多晶硅在氧化物区域上的突起。 在所形成的多晶硅的平坦表面上沉积氮化硅层，形成将形成垂直于氧化物区域的浮栅的位置的细长开口。 氮化硅中的开口中的暴露的多晶硅被氧化到至少下面的氧化硅区域的水平，并且去除了氮化硅层。 然后使用氧化硅层作为蚀刻阻挡层去除多晶硅层，并且所得多晶硅浮栅的边缘表面被氧化。 第二多晶硅层沉积在衬底上，并且形成平行且部分地与浮动栅极重叠的细长字线。 在衬底中形成源极线，并且形成覆盖浮栅的栅极线。

公开(公告)号：US6110780A

公开(公告)日：2000-08-29

申请号：US283842

申请日：1999-04-01

Applicant: Mo-Chiun Yu ,  Wen-Ting Chu ,  Syun-Min Jang

Inventor： Mo-Chiun Yu ,  Wen-Ting Chu ,  Syun-Min Jang

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  Y10S438/981

Abstract: A new method of using a NO or N.sub.2 O treatment on a first area on a wafer in order to form a thinner oxide film in the first area and a thicker oxide film in a second area on a wafer using a single oxidation step is achieved. A semiconductor substrate of a silicon wafer is provided wherein a first area is separated from a second area by an isolation region. The silicon substrate in the second area is treated with NO or N.sub.2 O whereby a high-nitrogen silicon oxide layer is formed on the surface of semiconductor substrate in the second area. A tunnel window is defined in the first area and the oxide layer within the tunnel window is removed. The silicon wafer is oxidized whereby a tunnel oxide layer forms within the tunnel window and whereby a gate oxide layer is formed overlying the high-nitrogen silicon oxide layer in the second area. The tunnel oxide layer has a greater thickness than the combined thickness of the gate oxide layer and the high-nitrogen silicon oxide layer. A conducting layer is deposited and patterned overlying the tunnel oxide layer and the gate oxide layer and fabrication of the integrated circuit device is completed.

Abstract translation: 实现了使用单一氧化步骤在晶片上的第一区域上使用NO或N2O处理以在第一区域中形成较薄氧化物膜并在晶片上的第二区域中形成较厚氧化膜的新方法。 提供硅晶片的半导体衬底，其中第一区域与第二区域通过隔离区域分离。 用NO或N 2 O处理第二区域中的硅衬底，由此在第二区域中在半导体衬底的表面上形成高氮氧化硅层。 在第一区域中定义隧道窗口，并且去除隧道窗口内的氧化物层。 硅晶片被氧化，从而在隧道窗内形成隧道氧化层，由此在第二区域中形成覆盖高氮氧化硅层的栅氧化层。 隧道氧化物层的厚度大于栅极氧化物层和高氮氧化硅层的组合厚度。 导电层被沉积并图案覆盖隧道氧化物层和栅极氧化物层，并且完成了集成电路器件的制造。

公开(公告)号：US07951670B2

公开(公告)日：2011-05-31

申请号：US11368714

申请日：2006-03-06

Applicant: Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

Inventor： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

IPC: H01L21/336

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

Abstract translation: 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

公开(公告)号：US07785966B2

公开(公告)日：2010-08-31

申请号：US11614677

申请日：2006-12-21

Applicant: Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

Inventor： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC: H01L21/8247

CPC classification number: H01L21/28273 ,  Y10S438/981

Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

Abstract translation: 一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。 该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

公开(公告)号：US20100041194A1

公开(公告)日：2010-02-18

申请号：US12603779

申请日：2009-10-22

Applicant: Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

Inventor： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

Abstract: A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

Abstract translation: 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分地延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

公开(公告)号：US20090051413A1

公开(公告)日：2009-02-26

申请号：US11841122

申请日：2007-08-20

Applicant: Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Kuo-Wei Chu ,  Cheng-Hsiung Kuo ,  Jih-Chen Wang

Inventor： Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Kuo-Wei Chu ,  Cheng-Hsiung Kuo ,  Jih-Chen Wang

IPC: G05F3/02

CPC classification number: H02M3/073 ,  H02M2003/075

Abstract: A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.

Abstract translation: 提供一种电荷泵电路，其包括与具有用于接收输入电压的第一晶体管的前电荷泵级串联的至少两个电荷泵级，以及具有用于提供输出电压的第二晶体管的最后电荷泵级。 第一晶体管被配置为在第一阈值电压下操作，并且第二晶体管被配置为在不同于第一阈值电压的第二阈值电压下操作。

公开(公告)号：US20080121975A1

公开(公告)日：2008-05-29

申请号：US11592290

申请日：2006-11-03

Applicant: Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

Abstract translation: 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。