公开(公告)号：US06759302B1

公开(公告)日：2004-07-06

申请号：US10209433

申请日：2002-07-30

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L31119

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US06380104B1

公开(公告)日：2002-04-30

申请号：US09636582

申请日：2000-08-10

申请人： Mo-Chiun Yu

发明人： Mo-Chiun Yu

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for forming upon a semiconductor substrate employed within a microelectronics fabrication a composite gate insulating layer of MOS device comprising a silicon oxide dielectric layer and a high-K dielectric layer. The method employs thermal oxidation of a silicon semiconductor substrate to form an initial silicon oxide dielectric layer. A RPN plasma method is employed to form a layer of silicon nitride high-k dielectric material partly into the silicon oxide dielectric layer. The composite dielectric layer is dielectrically equivalent to the initial silicon oxide dielectric layer, with equivalent performance, reliability and manufacturability of the MOS device.

摘要翻译： 一种用于在微电子制造中采用的半导体衬底上形成包括氧化硅介电层和高K电介质层的MOS器件的复合栅极绝缘层的方法。 该方法采用硅半导体衬底的热氧化以形成初始氧化硅介电层。 采用RPN等离子体法，部分地形成氧化硅介电层中的氮化硅高k电介质材料层。 复合介电层介电等效于初始氧化硅介电层，具有MOS器件的性能，可靠性和可制造性。

公开(公告)号：US07118974B2

公开(公告)日：2006-10-10

申请号：US10831871

申请日：2004-04-26

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US20050042859A1

公开(公告)日：2005-02-24

申请号：US10961707

申请日：2004-10-08

申请人： Mo-Chiun Yu ,  Yuan-Hung Chiu

发明人： Mo-Chiun Yu ,  Yuan-Hung Chiu

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/31122 ,  H01L21/0276 ,  H01L21/31144 ,  H01L29/517

摘要： A method of forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a patterned gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

摘要翻译： 一种形成栅电极的方法，包括以下步骤。 提供了具有形成在其上的高k栅极电介质层的衬底。 在高k栅极电介质层上形成栅极层。 在栅极层上形成栅极ARC层。 栅极ARC层和栅极层被图案化以形成图案化的栅极ARC层和图案化的栅极层。 不在图案化栅极层下面的高k栅极电介质层被部分蚀刻，并且形成图案化栅极层的平滑暴露的上表面。 除去不在图案化栅极层下方的部分蚀刻的高k栅极电介质层部分以形成由图案化栅极层和蚀刻的高k栅极电介质层组成的栅电极。

公开(公告)号：US06171911B2

公开(公告)日：2001-01-09

申请号：US09395284

申请日：1999-09-13

申请人： Mo-Chiun Yu

发明人： Mo-Chiun Yu

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： A process for significantly reducing the thickness of and improving the quality and uniformity of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process. The native oxide forms on exposed silicon surfaces after selectively etching away regions of a first thicker gate oxide and prior to growing a thinner gate oxide. The thinner gate oxide used to form high performance devices is between about 15 and 50 Å thick. The native oxide which forms on the exposed silicon surfaces has an initial thickness of about 10 Å. After the selective regions have been patterned the wafer is cleaned using a totally HF free cleaning procedure and subjected to a low pressure rapid thermal annealing between about 600 and 1,050° C. in an ambient of H2 and N2. The residual oxide thickness is reduced to about 4 Å with an accompanying improvement in thickness uniformity and oxide quality. The residual film is more robust that the initial native oxide and forms a much smaller thickness component of the final thinner gate oxide. After the annealing treatment, the residual native oxide becomes a more robust form of silicon oxide.

摘要翻译： 一种显着降低厚度并提高在双重厚度栅氧化层工艺中在硅晶片上形成MOSFET器件期间形成的自然氧化膜的质量和均匀性的方法。 在选择性地蚀刻第一较厚栅极氧化物的区域之后并且在生长更薄的栅极氧化物之前，在暴露的硅表面上形成天然氧化物。 用于形成高性能器件的较薄栅极氧化物的厚度约为15至50埃。 在暴露的硅表面上形成的天然氧化物具有约10埃的初始厚度。 在图案化选择区域之后，使用完全无HF的清洁程序清洁晶片，并在H 2和N 2的环境中进行约600至1050℃的低压快速热退火。 残余的氧化物厚度减小到约4，伴随着厚度均匀性和氧化物质量的改善。 残留的膜比初始的自然氧化物更坚固，并形成最终更薄的栅极氧化物的厚度分量更小的厚度。 在退火处理之后，残余的自然氧化物变成更坚固的氧化硅形式。

公开(公告)号：US06767847B1

公开(公告)日：2004-07-27

申请号：US10187704

申请日：2002-07-02

申请人： Chien-Ming Hu ,  Chien-Hao Chen ,  Mo-Chiun Yu ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Chien-Ming Hu ,  Chien-Hao Chen ,  Mo-Chiun Yu ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L21324

CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/2686 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method of forming a silicon nitride-silicon dioxide composite insulator layer for use as a gate insulator stack for an MOSFET device, has been developed. The method features formation of the silicon dioxide component of the gate insulator stack, after formation of the overlying silicon nitride component, allowing the gate insulator stack to be comprised with a nitrogen profile presenting enhanced barrier characteristic and less interface charge than counterpart silicon nitride-silicon dioxide composites formed wherein the silicon nitride component was deposited on an already grown underlying silicon dioxide layer. Oxygen ions, or oxygen radicals obtained via ultra-violet procedures, penetrate the silicon nitride component and locate in a top portion of the semiconductor substrate. Subsequent annealing allows reaction of the oxygen ions or radicals with a top portion of the semiconductor substrate resulting in the desired silicon dioxide component underlying silicon nitride.

摘要翻译： 已经开发了形成用作MOSFET器件的栅极绝缘体堆叠的氮化硅 - 二氧化硅复合绝缘体层的方法。 该方法在形成上覆氮化硅组分之后形成栅极绝缘体叠层的二氧化硅组分，允许栅极绝缘体堆叠包含具有增强的势垒特性和较少的对应氮化硅 - 硅的界面电荷的氮分布 形成二氧化硅复合物，其中氮化硅组分沉积在已经生长的下层二氧化硅层上。 通过紫外线工艺获得的氧离子或氧自由基穿透氮化硅组分并位于半导体衬底的顶部。 随后的退火允许氧离子或自由基与半导体衬底的顶部部分反应，导致氮化硅下面所需的二氧化硅组分。

公开(公告)号：US06362085B1

公开(公告)日：2002-03-26

申请号：US09619029

申请日：2000-07-19

申请人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518

摘要： A process for forming a nitrogen enriched ultra thin gate oxide is described. The nitrogen enrichment increases the dielectric constant of the gate oxide thereby decreasing it's effective oxide thickness. This in turn enhances the performance of MOSFET devices formed thereon. The nitrogen enrichment is accomplished by first enriching the surface of a silicon wafer with nitrogen by implanting nitrogen atoms into the silicon through a sacrificial screen oxide. After fixing the nitrogen by annealing, a nitrogen enriched gate oxide is thermally grown. Additional nitrogen is then infused into the gate oxide by remote plasma nitridation. This two step nitrogen enrichment process increases the dielectric constant of the gate oxide by a significant amount, approaching that of silicon nitride which not only decreases it's effective thickness with respect to gate capacitance, but also lowers device leakage by suppressing hot carrier injection over device drain regions. In addition, because the initial silicon surface is nitrogen rich, the thermal oxidation rate is reduced. The reduction of oxidation rate improves process control by making the oxidation time and temperature more manageable. A further benefit nitrogen of enrichment of the gate oxide is improvement of the durability of the gate oxide when used as an etch stop during polysilicon gate patterning.

摘要翻译： 描述了形成富氮超薄栅极氧化物的方法。 氮富集增加了栅极氧化物的介电常数，从而降低了其有效的氧化物厚度。 这反过来又增强了在其上形成的MOSFET器件的性能。 氮富集通过首先通过将氮原子注入到硅中通过牺牲屏蔽氧化物而用氮富集硅晶片的表面来实现。 在通过退火固定氮气之后，热生长富氮栅极氧化物。 然后通过远程等离子体氮化将额外的氮气输入到栅极氧化物中。 这种两步氮富集工艺使栅极氧化物的介电常数增加了大量，接近氮化硅的介电常数，这不仅降低了栅极电容的有效厚度，而且通过抑制器件漏极上的热载流子注入来降低器件泄漏 地区。 另外，由于初始硅表面富含氮，所以热氧化速率降低。 氧化速率的降低通过使氧化时间和温度更易于管理来改善过程控制。 栅极氧化物富集氮的另一个优点是当在多晶硅栅极图案化期间用作蚀刻停止时，提高了栅极氧化物的耐久性。

公开(公告)号：US06323143B1

公开(公告)日：2001-11-27

申请号：US09534161

申请日：2000-03-24

申请人： Mo-Chiun Yu

发明人： Mo-Chiun Yu

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device areas on a silicon substrate, an ultra-thin silicon nitride-oxide insulating layer is formed in two process steps. In the first process step a silicon nitride layer is formed on the device areas on the substrate using a low-pressure rapid thermal process (LP-RTP) and a reactant gas of ammonia (NH3) while insuring that the RTP tool is free of oxygen. Then a second process step is carried out sequentially in the same LP-RTP at an elevated temperature and using an oxygen-rich ambient (dinitrogen oxide N2O) as a reoxidation gas. The non-self-limiting characteristic of the ultra-thin-silicon nitride layer results in the controllable diffusion of the dissociated oxygen (O) and nitrous oxide (NO) through the silicon nitride layer to form a thin good quality silicon oxide layer on and in the substrate surface.

摘要翻译： 实现了用于场效应晶体管（FET）的改进的超薄氮化硅 - 氧化物栅绝缘层的方法。 在形成场氧化物以电隔离硅衬底上的器件区域之后，在两个工艺步骤中形成超薄氮氧化硅绝缘层。 在第一工艺步骤中，使用低压快速热处理（LP-RTP）和氨（NH 3）的反应气体在衬底上的器件区域上形成氮化硅层，同时确保RTP工具不含氧 。 然后在相同的LP-RTP中在升高的温度下依次进行第二工艺步骤，并且使用富氧环境（二氧化氮N 2 O）作为再氧化气体。 超薄氮化硅层的非自限制特性导致解离的氧（O）和一氧化二氮（NO）通过氮化硅层的可控扩散，以在其上形成薄的优质氧化硅层 在基板表面。

公开(公告)号：US06184155B2

公开(公告)日：2001-02-06

申请号：US09596902

申请日：2000-06-19

申请人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Mong-Song Liang

发明人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Mong-Song Liang

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/28211 ,  H01L21/31662

摘要： A process for forming an ultra-thin, silicon dioxide, gate insulator layer, for narrow channel length MOSFET devices, has been developed. The process features the use of a two step, in situ steam generated, (ISSG), procedure, to grow a silicon dioxide layer at a physical thickness between about 10 to 20 Angstroms, offering a gate insulator layer with a reduction in leakage current, during standby, or operating modes, when compared to counterpart silicon dioxide layers, formed without the use of the two step, ISSG procedure. The two step, ISSG procedure is comprised of a first step, featuring a steam oxidation, and an in situ anneal, in a nitrous oxide ambient, followed by the second step of the two step, ISSG procedure, performed in situ, in the same furnace used for the first step of the two step, ISSG procedure, with the second step of the two step, ISSG procedure again comprised of a steam oxidation, followed by an in situ anneal, performed in a nitrous oxide ambient.

摘要翻译： 已经开发了用于形成用于窄沟道长度MOSFET器件的超薄二氧化硅栅极绝缘体层的工艺。 该方法的特征在于使用两步，原位蒸汽生成（ISSG）方法，以在约10至20埃之间的物理厚度生长二氧化硅层，从而提供具有减小的漏电流的栅极绝缘体层， 在待机或操作模式下，与对应的二氧化硅层进行比较时，不使用两步即可形成ISSG程序。 两步ISSG程序包括第一步，其特征在于在一氧化二氮环境中进行蒸汽氧化和原位退火，随后是两步的第二步，ISSG程序，原位进行，在相同的 炉用于两步的第一步，ISSG程序，第二步是两步，ISSG程序再次由蒸汽氧化组成，随后在一氧化二氮环境中进行原位退火。

公开(公告)号：US07138317B2

公开(公告)日：2006-11-21

申请号：US10831874

申请日：2004-04-26

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

摘要翻译： 在由衬底上的STI隔离区隔开的有源区上形成多个栅极氧化物厚度的方法。 将第一层氧化物生长至约50埃的厚度，然后除去选定的区域。 生长比第一生长氧化物薄的第二层氧化物。 对于三种不同的栅极氧化物厚度，选择的第二氧化物生长区域用N 2 O 3等离子体氮化，这增加了栅极氧化物的介电常数并降低了有效的氧化物厚度。 为了实现四种不同的栅极氧化物厚度，对所选择的第一生长氧化物和选择的第二生长氧化物区域进行氮化。 栅极氧化物的氮化还防止杂质掺杂剂跨过栅极氧化物层迁移并减少待机电流的泄漏。 该方法还减少由HF蚀刻剂引起的STI区域的拐角损失。