ANALOG CIRCUIT DIFFERENTIAL PAIR ELEMENT MISMATCH DETECTION USING SPECTRAL SEPARATION

    公开(公告)号:US20220190789A1

    公开(公告)日:2022-06-16

    申请号:US17119228

    申请日:2020-12-11

    Abstract: A method for use in an analog circuit having a plurality of differential pairs of elements, wherein for each pair of the plurality of differential pairs of elements, the elements of the pair are designed to match but may have mismatch that induces error. The method includes, for each pair of at least two pairs of the plurality of differential pairs of elements: spectrally separating the mismatch-induced error of the pair from mismatch-induced error of a remainder of the plurality of differential pairs of elements, monitoring, by an analog-to-digital converter (ADC), an output of the analog circuit, and analyzing the monitored output to measure the mismatch-induced error of the pair.

    High common mode rejection ratio (CMRR) current monitoring circuit using floating supplies

    公开(公告)号:US11296666B1

    公开(公告)日:2022-04-05

    申请号:US16796475

    申请日:2020-02-20

    Abstract: A high CMRR current monitoring circuit includes a first stage that receives a current sense signal, a voltage across a current sense resistor in series with an output of a class-D amplifier. First stage is powered by at least one floating supply and/or reference that tracks the amplifier output. First stage applies gain to the current sense signal to generate an intermediate signal. A second stage receives the intermediate signal and is powered by a ground-referenced supply and provides an amplified representation of the current sense signal. The floating supply is supplied by a capacitive-coupled power source driven by the ground-referenced supply. The second stage output may be a voltage relative to ground or a digital signal. The intermediate signal may be a current, digital signal, or amplified version of the current sense signal voltage. The first stage may be a transconductance amplifier and the second stage a transimpedance amplifier.

    Calibration of digital-to-analog converter with low pin count

    公开(公告)号:US11239857B2

    公开(公告)日:2022-02-01

    申请号:US16943156

    申请日:2020-07-30

    Inventor: John L. Melanson

    Abstract: An open-loop digital-to-analog converter (DAC) circuit may include a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to inputs of the plurality of DAC elements, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator.

    SDR-based adaptive noise cancellation (ANC) system

    公开(公告)号:US10720138B2

    公开(公告)日:2020-07-21

    申请号:US15495746

    申请日:2017-04-24

    Abstract: The overall performance of an ANC system may be improved by configuring the ANC system to perform adaption in the frequency domain. The ANC systems may be configured to update an algorithm of an adaptive filter based, at least in part, on the first input signal, the second input signal, and a feedback signal that is based on an output of the adaptive filter. Updating may include changing parameters of the algorithm based on a SDR based, at least in part, on the first input signal. Updating may also include normalizing a step size and processing at least full band information for the input signal in a frequency domain to generate coefficient values for the algorithm. Updating may also include applying a frequency domain magnitude constraint on adaptive filter coefficients.

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