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公开(公告)号：US11653150B2
公开(公告)日：2023-05-16
申请号：US17516830
申请日：2021-11-02
发明人： John Paul Lesso , Mark James McCloy-Stevens , John Bruce Bowlerwell , Yanto Suryono , Xin Zhao , Morgan Timothy Prior
CPC分类号： H04R5/04 , H03F3/183 , H03G3/3005 , H04R5/02 , H04R29/001 , H04S1/007 , H03G2201/103
摘要： This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.
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公开(公告)号：US11552567B2
公开(公告)日：2023-01-10
申请号：US17218992
申请日：2021-03-31
发明人： Xin Zhao , Jun Yan , Xiaofan Fei , Mark May , John L. Melanson
摘要： A single-inductor multiple output (SIMO) switched-power DC-DC converter for a class-D amplifier provides outputs that are symmetric about a common-mode input voltage of the amplifier, while remaining asymmetric about a return terminal of the amplifier and switching converter. The DC-DC converter includes an inductive element, a switching circuit that energizes the inductive element from an input source, and a control circuit that controls the switching circuit. The control circuit may have multiple switching modes, and in one of the multiple switching modes, the switching circuit may couple the inductive element between outputs of the converter so that stored energy produces a differential change between the voltages of the outputs. The control circuit may implement a first control loop that maintains a common mode voltage of the pair of outputs at a predetermined voltage independent of the individual voltages of the pair of outputs.
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公开(公告)号：US11522509B2
公开(公告)日：2022-12-06
申请号：US17194395
申请日：2021-03-08
发明人： Xin Zhao , Tejasvi Das , Xiaofan Fei
IPC分类号： H03F3/45
摘要： An operational amplifier with one or more fully-differential amplifier stages has a common-mode control input. A low-frequency feedback control path is coupled between an output of the fully-differential amplifier stages and the common-mode control input to control low-frequency drift of the common-mode voltage of the output of the stages. A high-frequency feed-forward control path couples a pair of inputs of the stages to control high-frequency ripple of a common-mode voltage of the inputs of the stages. One or more of the differential amplifier stages may have a bias input that controls a direct-current (DC) bias voltage of gates of pull-up transistors of the stage that is both DC and capacitively coupled to the gates so that the stage operates with class A bias at DC and with class AB bias at high frequencies.
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公开(公告)号：US20220286098A1
公开(公告)日：2022-09-08
申请号：US17194395
申请日：2021-03-08
发明人： Xin Zhao , Tejasvi Das , Xiaofan Fei
IPC分类号： H03F3/45
摘要： An operational amplifier with one or more fully-differential amplifier stages has a common-mode control input. A low-frequency feedback control path is coupled between an output of the fully-differential amplifier stages and the common-mode control input to control low-frequency drift of the common-mode voltage of the output of the stages. A high-frequency feed-forward control path couples a pair of inputs of the stages to control high-frequency ripple of a common-mode voltage of the inputs of the stages. One or more of the differential amplifier stages may have a bias input that controls a direct-current (DC) bias voltage of gates of pull-up transistors of the stage that is both DC and capacitively coupled to the gates so that the stage operates with class A bias at DC and with class AB bias at high frequencies.
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公开(公告)号：US10726873B2
公开(公告)日：2020-07-28
申请号：US16103288
申请日：2018-08-14
发明人： Ku He , Tejasvi Das , Xin Zhao , Xiaofan Fei
IPC分类号： G11B27/034 , G11B27/19
摘要： A polymorphic playback system is disclosed in which one or more parameters of a signal path of the polymorphic playback system are varied based on one or more characteristics of a playback signal processed by the signal path, wherein the polymorphic playback system may include a lower-latency detection filter, a higher-latency detection filter, and a control subsystem that uses the lower-latency detection filter for detecting the one or more first characteristics of the playback signal and uses the higher-latency detection filter for detecting the one or more second characteristics of the playback signal.
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公开(公告)号：US10701486B1
公开(公告)日：2020-06-30
申请号：US16522439
申请日：2019-07-25
发明人： John L. Melanson , Xiaofan Fei , Lei Zhu , Xin Zhao , Wei-Shun Shum , Leyi Yin , Ku He , Johann G. Gaboriau
IPC分类号： H04R3/04
摘要： A system may include a filter configured to receive a digital audio input signal quantized at between two and 257 quantization levels and sampled at at least 500 kilohertz, the filter further configured to perform filtering on the digital audio input signal to generate a filtered digital audio input signal, the filter having a selectable variable group delay, a digital-to-analog converter configured to receive the filtered digital audio input signal and convert the filtered digital audio input signal into an equivalent analog audio input signal, and a driver configured to receive the equivalent analog audio input signal and drive an analog audio output signal to a transducer.
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公开(公告)号：US10658988B1
公开(公告)日：2020-05-19
申请号：US15943125
申请日：2018-04-02
发明人： Miao Song , Xiaofan Franky Fei , Xin Zhao , Tejasvi Das , Lei Zhu , Jing Bai , Alan Mark Morton
摘要： A signal processing system may include a modulation stage configured to generate a modulated input signal, an open-loop switched mode driver coupled to the modulation stage and configured to generate an output signal from the modulated input signal, a voltage regulator configured to generate a supply voltage that supplies electrical energy to the open-loop switched mode driver, and a control subsystem configured to, when a magnitude of the modulated input signal falls below a threshold magnitude, control the voltage regulator to control the supply voltage such that the output signal varies non-linearly with the modulated input signal for magnitudes of the modulated input signal below the threshold magnitude.
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公开(公告)号：US10181845B1
公开(公告)日：2019-01-15
申请号：US15927691
申请日：2018-03-21
发明人： Tejasvi Das , Alan Mark Morton , Xin Zhao , Lei Zhu , Xiaofan Fei , Johann G. Gaboriau , John L. Melanson , Amar Vellanki
摘要： A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
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公开(公告)号：US20180212570A1
公开(公告)日：2018-07-26
申请号：US15581057
申请日：2017-04-28
发明人： Lei Zhu , Xin Zhao , John L. Melanson
CPC分类号： H03F1/0233 , H03F1/30 , H03F1/3247 , H03F1/3264 , H03F1/56 , H03F3/183 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2175 , H03F2200/03 , H03F2200/351 , H03F2200/387 , H03F2200/391 , H03F2200/421 , H03F2200/459 , H03F2201/3233 , H03G3/3005 , H03G3/3089 , H03M1/66
摘要： Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
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公开(公告)号：US10727860B1
公开(公告)日：2020-07-28
申请号：US16522033
申请日：2019-07-25
发明人： Wai-Shun Shum , Lei Zhu , Johann G. Gaboriau , Xiaofan Fei , Xin Zhao
IPC分类号： H03M3/00
摘要： A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.
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