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    Current digital-to-analog converter with warming of digital-to-analog converter elements
    2.
    发明授权
    Current digital-to-analog converter with warming of digital-to-analog converter elements 有权

    公开(公告)号：US11043959B1

    公开(公告)日：2021-06-22

    申请号：US16942062

    申请日：2020-07-29

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： John L. Melanson ,  Johann G. Gaboriau ,  Lei Zhu ,  Wai-Shun Shum ,  Xiaofan Fei ,  Leyi Yin

    IPC: H03M1/74 ,  H04R3/00 ,  H03M3/00

    Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

    Low-latency audio output with variable group delay
    4.
    发明授权
    Low-latency audio output with variable group delay 有权

    公开(公告)号：US10701486B1

    公开(公告)日：2020-06-30

    申请号：US16522439

    申请日：2019-07-25

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： John L. Melanson ,  Xiaofan Fei ,  Lei Zhu ,  Xin Zhao ,  Wei-Shun Shum ,  Leyi Yin ,  Ku He ,  Johann G. Gaboriau

    IPC: H04R3/04

    Abstract: A system may include a filter configured to receive a digital audio input signal quantized at between two and 257 quantization levels and sampled at at least 500 kilohertz, the filter further configured to perform filtering on the digital audio input signal to generate a filtered digital audio input signal, the filter having a selectable variable group delay, a digital-to-analog converter configured to receive the filtered digital audio input signal and convert the filtered digital audio input signal into an equivalent analog audio input signal, and a driver configured to receive the equivalent analog audio input signal and drive an analog audio output signal to a transducer.

    Calibration of a dual-path pulse width modulation system
    6.
    发明授权
    Calibration of a dual-path pulse width modulation system 有权

    公开(公告)号：US10181845B1

    公开(公告)日：2019-01-15

    申请号：US15927691

    申请日：2018-03-21

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Tejasvi Das ,  Alan Mark Morton ,  Xin Zhao ,  Lei Zhu ,  Xiaofan Fei ,  Johann G. Gaboriau ,  John L. Melanson ,  Amar Vellanki

    IPC: H03K7/08 ,  H02M3/157 ,  G06F1/025

    Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

    Gain control in a class-D open-loop amplifier
    8.
    发明授权
    Gain control in a class-D open-loop amplifier 有权

    公开(公告)号：US10763811B2

    公开(公告)日：2020-09-01

    申请号：US16181762

    申请日：2018-11-06

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Lei Zhu ,  Tejasvi Das ,  John L. Melanson ,  Wai-shun Wilson Shum ,  Jing Bai ,  Xin Zhao ,  Xiaofan Fei

    IPC: H03G3/30 ,  H03F3/217 ,  H03F3/187 ,  H03F3/387

    Abstract: A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

    Digital short detection method of class D amplifier
    9.
    发明授权
    Digital short detection method of class D amplifier 有权

    公开(公告)号：US10663531B2

    公开(公告)日：2020-05-26

    申请号：US16156069

    申请日：2018-10-10

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Lei Zhu ,  Jing Bai ,  Xiaofan Fei ,  Xin Zhao

    IPC: G01R31/50 ,  H03F3/217

    Abstract: An apparatus detects a short of a class-D amplifier. A pulse detector detects an output PWM pulse exceeds a predetermined width and a controller differentiates whether the pulse width exceeding is caused by a short or by a large digital input signal occurring during normal operation based on an expected level of the digital input signal to a level of the digital input signal when the pulse width exceeds the predetermined width. The expected level is dynamically obtained in response to one or more previous PWM pulses exceeding the predetermined width during the normal operation and may be selected based on an amount the pulse exceeds the predetermined width. A lookup table of predetermined levels, selected based on impedance of a load, provides the expected level if the expected level has not yet been dynamically obtained when the pulse width exceeds.

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