CLASS-D AMPLIFIER CIRCUITS
    41.
    发明申请
    CLASS-D AMPLIFIER CIRCUITS 有权
    CLASS-D放大器电路

    公开(公告)号:US20170019079A1

    公开(公告)日:2017-01-19

    申请号:US15278862

    申请日:2016-09-28

    Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.

    Abstract translation: 具有提高功率效率的D类放大器电路的方法和装置。 电路具有至少具有第一和第二开关的输出级和接收要被放大的输入信号SIN和第一时钟信号fSW的调制器。 调制器基于输入信号在开关周期内控制第一和第二开关的占空比,其中开关周期具有基于第一时钟信号的开关频率。 频率控制器响应于输入信号的幅度的指示来控制第一时钟信号的频率,以便提供第一输入信号幅度的第一开关频率和在第二输入信号幅度下的第二,较低开关频率 ,输入信号幅度。 在低信号幅度下可以容忍较低的开关频率,并且以这种方式改变开关频率,从而在降低开关功率损耗的同时保持稳定性。

    Voltage regulators
    42.
    发明授权

    公开(公告)号:US12169418B2

    公开(公告)日:2024-12-17

    申请号:US18323530

    申请日:2023-05-25

    Abstract: This application relates to voltage regulators and, particular, to low-dropout regulators (LDOs). The regulator (300) has an output stage (102) which receives an input voltage (Vin) and outputs an output voltage (Vout) and which includes at least one transistor (103) as an output device configured to pass an output current to the output, based on a drive voltage (V1). A differential amplifier (101) is configured to receive a feedback signal derived from the output voltage and also a reference voltage (REF) to generate an amplifier output to control the drive voltage (V1) to minimise any difference between the feedback signal and the reference voltage. A controller (301) is operable to selectively reconfigure the output stage to provide a change in output current in response to a load activity signal (ACT), which is indicative of a change in load activity that results in a change in load current demand for a load connected, in use, to the output.

    Driver circuitry
    45.
    发明授权

    公开(公告)号:US11958075B2

    公开(公告)日:2024-04-16

    申请号:US17092613

    申请日:2020-11-09

    CPC classification number: B06B1/0223 B06B1/06 H03K17/30 B06B2201/55

    Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises driver circuitry configured to generate a drive signal, based on an input signal to the driver circuitry, for driving the load, and commutator circuitry for coupling the driver circuitry to the load. The commutator circuitry is configured to alternate between commutation states in response to a level of the drive signal meeting a drive signal threshold or in response to a level of the input signal meeting a first input signal threshold. The circuitry is configured to apply an offset to the input signal when the input signal is below a second input signal threshold so as to increase a minimum level of the drive signal above the drive signal threshold or to increase a minimum level of the input signal above the first input signal threshold.

    Authenticating received speech
    46.
    发明授权

    公开(公告)号:US11894000B2

    公开(公告)日:2024-02-06

    申请号:US17721698

    申请日:2022-04-15

    Inventor: John P. Lesso

    CPC classification number: G10L17/22 G10L17/06 G10L17/10 G10L17/26 G10L25/06

    Abstract: A speech signal is received by a device comprising first and second transducers, and the first transducer comprises a microphone. A method comprises performing a first voice biometric process on speech contained in a first part of a signal received by the microphone, in order to determine whether the speech is the speech of an enrolled user. A first correlation is determined, between said first part of the signal received by the microphone and a corresponding part of the signal received by the second transducer. A second correlation is determined, between said second part of the signal received by the microphone and the corresponding part of the signal received by the second transducer. It is then determined whether the first correlation and the second correlation satisfy a predetermined condition. If it is determined that the speech contained in the first part of the received signal is the speech of an enrolled user and that the first correlation and the second correlation satisfy the predetermined condition, the received speech signal is authenticated.

    Circuitry for analyte measurement
    47.
    发明授权

    公开(公告)号:US11846600B2

    公开(公告)日:2023-12-19

    申请号:US17463796

    申请日:2021-09-01

    CPC classification number: G01N27/3273 G01R19/165 G01R19/16566

    Abstract: Circuitry for measuring a characteristic of an electrochemical cell, the circuitry comprising: a comparator having a first comparator input, a second comparator input and a comparator output; a feedback path between the comparator output and the second comparator input configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate the feedback signal, wherein the loop filter comprises the electrochemical cell.

    Time encoding modulator circuitry
    50.
    发明授权

    公开(公告)号:US11509272B2

    公开(公告)日:2022-11-22

    申请号:US17319620

    申请日:2021-05-13

    Abstract: This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.

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