公开(公告)号：US20120094456A1

公开(公告)日：2012-04-19

申请号：US13336191

申请日：2011-12-23

申请人： Ta-Wei Wang ,  Chih-Sheng Chang

发明人： Ta-Wei Wang ,  Chih-Sheng Chang

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/78603 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78654

摘要： A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

摘要翻译： 半导体器件包括栅极堆叠; 门叠下的气隙; 垂直于栅极堆叠和气隙之间的半导体层; 以及在半导体层下面和毗邻的第一介电层。 第一介电层暴露于气隙。

公开(公告)号：US08106468B2

公开(公告)日：2012-01-31

申请号：US12143612

申请日：2008-06-20

申请人： Ta-Wei Wang ,  Chih-Sheng Chang

发明人： Ta-Wei Wang ,  Chih-Sheng Chang

IPC分类号： H01L21/764

CPC分类号： H01L29/78603 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78654

摘要： A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

摘要翻译： 半导体器件包括栅极堆叠; 门叠下的气隙; 垂直于栅极堆叠和气隙之间的半导体层; 以及在半导体层下面和毗邻的第一介电层。 第一介电层暴露于气隙。

公开(公告)号：US07990354B2

公开(公告)日：2011-08-02

申请号：US12069922

申请日：2008-02-12

申请人： Chih-Sheng Chang ,  Chueh-Ju Chen

发明人： Chih-Sheng Chang ,  Chueh-Ju Chen

IPC分类号： G09G3/38

CPC分类号： G09G3/3688 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2340/16 ,  G09G2360/18

摘要： An exemplary LCD (200) includes gate lines (23), data lines (24); a gradation voltage adjusting circuit (26) for receiving the gradation voltages respectively corresponding to the j, j+1, k, and k+1 frames interchanging the j+1 frame gradation voltage and the k frame gradation voltage when a first voltage difference between j frame gradation voltage and j+1 frame gradation voltage is less than a second voltage difference between j frame gradation voltage and k frame gradation voltage; a memory circuit (28) for storing the gradation voltages corresponding to the frames 1, 2, . . . j, j+2, . . . k−1, k+1 . . . h and storing the interchanged gradation voltages corresponding to the frames j+1 and k; and a gate driver (21) for receiving the gradation voltages stored in the memory circuit. A smallest rectangular area formed by any two adjacent gate lines together with any two adjacent data lines defines a pixel unit thereat.

摘要翻译： 示例性LCD（200）包括栅极线（23），数据线（24）; 灰度电压调整电路（26），用于在第j + 1帧灰度级电压和k帧灰度级电压之间分别对应于j + 1，k和+ j帧灰度电压和j + 1帧灰度电压小于j帧灰度电压和k帧灰度电压之间的第二电压差; 存储电路（28），用于存储与帧1,2对应的灰度电压。 。 。 j，j + 2，。 。 。 k-1，k + 1。 。 。 h并存储对应于帧j + 1和k的互换灰度电压; 以及用于接收存储在存储电路中的灰度电压的栅极驱动器（21）。 由任何两个相邻的栅极线与任何两个相邻的数据线一起形成的最小矩形区域在其上限定像素单元。

公开(公告)号：US20100213575A1

公开(公告)日：2010-08-26

申请号：US12715103

申请日：2010-03-01

申请人： Shuo-Mao Chen ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Hua-Chou Tseng

发明人： Shuo-Mao Chen ,  Chih-Ping Chao ,  Chih-Sheng Chang ,  Hua-Chou Tseng

IPC分类号： H01L27/082

CPC分类号： H01L29/0692 ,  H01L21/8224 ,  H01L27/0203 ,  H01L27/0821 ,  H01L29/735

摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.

摘要翻译： 横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。 与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。 第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。 具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。

公开(公告)号：US07701038B2

公开(公告)日：2010-04-20

申请号：US11589478

申请日：2006-10-30

申请人： Shuo-Mao Chen ,  Chih-Ping Chao ,  Chih-Sheng Chang

发明人： Shuo-Mao Chen ,  Chih-Ping Chao ,  Chih-Sheng Chang

IPC分类号： H01L21/8249 ,  H01L21/331 ,  H01L21/70 ,  H01L21/02

CPC分类号： H01L29/0692 ,  H01L29/735

摘要： A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.

摘要翻译： 提供了具有改善的电流增益的横向双极结型晶体管及其形成方法。 晶体管包括形成在衬底上的第一导电类型的阱区，在阱区中与第一导电类型相反的第二导电类型的至少一个发射极，其中至少一个发射极中的每一个互连，多个集电极 在阱区域中的第二导电类型，其中集电器彼此互连，以及在阱区中的第一导电类型的多个基极接触，其中基极触点彼此互连。 优选地，至少一个发射器的所有侧面都与集电体相邻，并且基极触点都不邻近发射器的侧面。 相邻的发射极，集电极和基极触点由阱区中的间隔隔开。

公开(公告)号：US20080248623A1

公开(公告)日：2008-10-09

申请号：US11784721

申请日：2007-04-09

申请人： Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

发明人： Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823892 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  Y10S438/919

摘要： A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.

摘要翻译： 一种用于形成高电压漏极金属氧化物半导体（HVD-MOS）器件的方法包括：提供半导体衬底; 形成第一导电类型的阱区; 以及在所述半导体衬底中并且仅在所述HVD-MOS器件的漏极侧上形成嵌入阱区域，其中所述嵌入区域是与所述第一导电类型相反的第二导电类型。 形成嵌入阱区的步骤包括同时掺杂嵌入阱区和芯规则MOS器件的阱区，并同时掺杂I / O规则MOS器件的嵌入阱区和阱区，其中核和 I / O常规MOS器件是第一导电类型。 所述方法还包括形成从所述嵌入阱区域上方延伸到所述阱区域的栅极堆叠。

公开(公告)号：US20070105301A1

公开(公告)日：2007-05-10

申请号：US11589478

申请日：2006-10-30

申请人： Shuo-Mao Chen ,  Chih-Ping Chao ,  Chih-Sheng Chang

发明人： Shuo-Mao Chen ,  Chih-Ping Chao ,  Chih-Sheng Chang

IPC分类号： H01L21/8249 ,  H01L21/331

CPC分类号： H01L29/0692 ,  H01L29/735

摘要： A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.

摘要翻译： 提供了具有改善的电流增益的横向双极结型晶体管及其形成方法。 晶体管包括形成在衬底上的第一导电类型的阱区，在阱区中与第一导电类型相反的第二导电类型的至少一个发射极，其中至少一个发射极中的每一个互连，多个集电极 在阱区域中的第二导电类型，其中集电器彼此互连，以及在阱区中的第一导电类型的多个基极接触，其中基极触点彼此互连。 优选地，至少一个发射器的所有侧面都与集电体相邻，并且基极触点都不邻近发射器的侧面。 相邻的发射极，集电极和基极触点由阱区中的间隔隔开。

公开(公告)号：US20070085817A1

公开(公告)日：2007-04-19

申请号：US11580508

申请日：2006-10-13

申请人： Eddy(Ging-Li) Chen ,  Long-Kuan Chen ,  Sz Chen ,  Chih-Sheng Chang ,  Wen-Chieh Liao ,  Chueh-Ju Chen ,  Tsau Hsieh

发明人： Eddy(Ging-Li) Chen ,  Long-Kuan Chen ,  Sz Chen ,  Chih-Sheng Chang ,  Wen-Chieh Liao ,  Chueh-Ju Chen ,  Tsau Hsieh

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/2025 ,  G09G3/3406 ,  G09G2320/0646

摘要： A method for driving a liquid crystal display (200) includes: providing a liquid crystal display having a plurality of pixel units and a backlight; dividing a frame time into a plurality of sub-frames; defining each pixel unit to have two states, namely on or off, in each of the sub-frames; defining the backlight to have a gradation luminance and two states, namely on or off, in each of the sub-frames; and synchronously controlling the state of each pixel unit, a time period of the on state of each pixel unit, the gradation luminance of the backlight, and a time period of the on state of the backlight in each of the sub-frames to make a resulting total luminous flux in each pixel unit corresponding to a gray scale of an image to be displayed in the frame time to be the same as that of other pixel units.

摘要翻译： 一种用于驱动液晶显示器（200）的方法包括：提供具有多个像素单元和背光的液晶显示器; 将帧时间划分成多个子帧; 将每个像素单元定义为在每个子帧中具有两个状态，即开或关; 将背光源定义为具有每个子帧中的灰度亮度和两个状态，即开/关; 同时控制每个像素单元的状态，每个像素单元的接通状态的时间段，背光的灰度亮度和每个子帧中的背光的接通状态的时间段，以使 使得在帧时间中要显示的图像的灰度对应的每个像素单元中的总光通量与其它像素单元的相同。

公开(公告)号：US20060142938A1

公开(公告)日：2006-06-29

申请号：US11115266

申请日：2005-04-27

申请人： Chih-Hung Lin ,  Chih-Sheng Chang

发明人： Chih-Hung Lin ,  Chih-Sheng Chang

IPC分类号： G01C21/00

CPC分类号： G01C22/006

摘要： An inertial positioning system is disclosed, which includes at least one sensor, an inertial processing unit, a step-distance determination module, a external positioning module, a Kalman filter and an output terminal, wherein the step-distance determinate module estimates an inertial step-distance via analyzing peak values of velocity and time intervals, and in addition, the external positioning module provides a precise initial state to effectively constrain error of the estimated step-distance.

摘要翻译： 公开了一种惯性定位系统，其包括至少一个传感器，惯性处理单元，步距确定模块，外部定位模块，卡尔曼滤波器和输出端子，其中步距确定模块估计惯性步骤 通过分析速度和时间间隔的峰值，并且外部定位模块提供精确的初始状态以有效地约束估计步距的误差。

公开(公告)号：US20050245013A1

公开(公告)日：2005-11-03

申请号：US10834125

申请日：2004-04-29

申请人： Chi-Rong Lin ,  Nien-Chung Jiang ,  Chih-Sheng Chang

发明人： Chi-Rong Lin ,  Nien-Chung Jiang ,  Chih-Sheng Chang

IPC分类号： C23C16/00 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L21/76814 ,  H01L21/02063

摘要： A method for manufacturing a complementary metal-oxide semiconductor sensor is provided. The present method provides a semiconductor structure including a plurality of conductors thereon. An inter-metal dielectric layer is formed on the conductors. A silicon nitride film is applied on the inter-metal dielectric layer. An oxide layer is formed on the silicon nitride film. The oxide layer, the silicon nitride film and the inter-metal dielectric are etched to expose portions of the conductors. The oxide layer and the exposed conductors are cleaned in a cleaning step later.

摘要翻译： 提供一种制造互补金属氧化物半导体传感器的方法。 本方法提供了包括多个导体的半导体结构。 在导体上形成金属间介电层。 在金属间电介质层上施加氮化硅膜。 在氮化硅膜上形成氧化物层。 蚀刻氧化物层，氮化硅膜和金属间电介质以暴露部分导体。 氧化物层和暴露的导体在稍后的清洁步骤中被清洁。