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公开(公告)号：US08324713B2
公开(公告)日：2012-12-04
申请号：US12715103
申请日：2010-03-01
IPC分类号： H01L29/735 , H01L29/732
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译： 横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。 与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。 第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。 具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。
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公开(公告)号：US20100213575A1
公开(公告)日：2010-08-26
申请号：US12715103
申请日：2010-03-01
IPC分类号： H01L27/082
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译： 横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。 与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。 第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。 具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。
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公开(公告)号：US08581347B2
公开(公告)日：2013-11-12
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译： 提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一集电极，第一基极和第一发射极。 第一集电器包括设置在衬底中的第一掺杂阱。 第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。 第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。 第二晶体管包括第二集电极，第二基极和第二发射极。 第二集电体包括衬底的掺杂部分。 第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。 第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。
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公开(公告)号：US20120018811A1
公开(公告)日：2012-01-26
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译： 提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一集电极，第一基极和第一发射极。 第一集电器包括设置在衬底中的第一掺杂阱。 第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。 第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。 第二晶体管包括第二集电极，第二基极和第二发射极。 第二集电体包括衬底的掺杂部分。 第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。 第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。
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公开(公告)号：US08971014B2
公开(公告)日：2015-03-03
申请号：US12984731
申请日：2011-01-05
申请人： Wei-Chun Hua , Chung-Long Chang , Chun-Hung Chen , Chih-Ping Chao , Jye-Yen Cheng , Hua-Chou Tseng
发明人： Wei-Chun Hua , Chung-Long Chang , Chun-Hung Chen , Chih-Ping Chao , Jye-Yen Cheng , Hua-Chou Tseng
IPC分类号： H01G4/228 , H01L49/02 , H01L23/522
CPC分类号： H01G4/005 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10T29/43 , H01L2924/00
摘要： A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.
摘要翻译： 电容器结构包括第一和第二组电极和多个线插头。 第一组电极具有形成在多个金属化层中的第一金属化层中的第一电极和第二电极，其中第一电极和第二电极被绝缘材料分开。 第二组电极具有形成在多个金属化层之间的第二金属化层中的第三电极和第四电极，其中第三电极和第四电极被绝缘材料隔开。 线插头将第二组电极连接到第一组电极。
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公开(公告)号：US08334187B2
公开(公告)日：2012-12-18
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/20
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译： 公开了制造诸如薄膜电阻器的集成电路器件的方法。 一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。
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公开(公告)号：US20110318898A1
公开(公告)日：2011-12-29
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/02
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译： 公开了制造诸如薄膜电阻器的集成电路器件的方法。 一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。
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公开(公告)号：US09620421B2
公开(公告)日：2017-04-11
申请号：US12948184
申请日：2010-11-17
申请人： Chien-Chih Ho , Chih-Ping Chao , Hua-Chou Tseng , Chun-Hung Chen , Chia-Yi Su , Alex Kalnitsky , Jye-Yen Cheng , Harry-Hak-Lay Chuang
发明人： Chien-Chih Ho , Chih-Ping Chao , Hua-Chou Tseng , Chun-Hung Chen , Chia-Yi Su , Alex Kalnitsky , Jye-Yen Cheng , Harry-Hak-Lay Chuang
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/8234 , H01L29/51 , H01L29/66
CPC分类号： H01L23/481 , H01L21/76802 , H01L21/76816 , H01L21/76895 , H01L21/823425 , H01L21/823475 , H01L21/823842 , H01L21/823871 , H01L27/088 , H01L29/0653 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.
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9.发明授权Method for fabricating a transformer integrated with a semiconductor structure 有权用于制造与半导体结构集成的变压器的方法公开(公告)号：US07367113B2
公开(公告)日：2008-05-06
申请号：US11278952
申请日：2006-04-06
IPC分类号： H01F41/02
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译： 提供基板，并在其上形成顶部互连金属层和初级绕组层。 然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。 在钝化层上形成次级绕组层和至少一个焊盘。 接合焊盘通过通孔电连接到顶部互连金属层。
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公开(公告)号：US20050212641A1
公开(公告)日：2005-09-29
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译： 公开了一种在其上具有介电层的基板上形成的电感器。 电感器包括第一电感器图案，第二电感器图案，第三电感器图案。 第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案， 第二电感器图案和第三电感器图案具有相似的图案。 因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。
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