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    Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions
    42.
    发明授权
    Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions 失效
    翻译后备缓冲区是响应于在能够处理推测性指令的微处理器内使用的错误而非阻塞的

    公开(公告)号：US5613083A

    公开(公告)日：1997-03-18

    申请号：US316089

    申请日：1994-09-30

    申请人： Andrew F. Glew ,  Haitham Akkary ,  Glenn J. Hinton

    发明人： Andrew F. Glew ,  Haitham Akkary ,  Glenn J. Hinton

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/684

    摘要： A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking in response to translation lookaside buffer misses requiring page table walks. Once a translation lookaside buffer miss is detected, a page table walk is initiated to satisfy the miss. During the page table walk, additional memory instructions are processed by the translation lookaside buffer. Any additional instructions which cause translation lookaside buffer hits are merely processed by the translation lookaside buffer. However, instructions causing translation lookaside buffer misses while the page table walk is being performed are blocked pending completion of the page table walk. Once the page table walk is completed the blocked instructions are reawakened and are again processed by the translation lookaside buffer. Global and selective wakeup mechanisms are described. An implementation wherein the non-blocking translation lookaside buffer is provided within a microprocessor capable of speculative and out-of-order processing is also described.

    摘要翻译： 描述了翻译后备缓冲器用于能够对存储器指令进行推测和无序处理的微处理器。 翻译后备缓冲区是响应于需要页表行进的翻译后备缓冲区错误而不阻塞的。 一旦检测到翻译后备缓存器未命中，则启动页表步行以满足缺失。 在页表行走期间，另外的存储器指令由翻译后备缓冲器处理。 导致翻译后备缓冲区命中的任何附加指令仅由翻译后备缓冲器处理。 然而，正在执行页表行进时导致翻译后备缓冲区未命中的指令在页表行进完成之前被阻止。 一旦页表行进完成，阻塞的指令被重新唤醒，并由翻译后备缓冲区再次处理。 描述了全局和选择性唤醒机制。 还描述了其中在能够进行推测和无序处理的微处理器内提供非阻塞转换后备缓冲器的实现。

    Method and apparatus for implementing a single clock cycle line replacement in a data cache unit
    44.
    发明授权
    Method and apparatus for implementing a single clock cycle line replacement in a data cache unit 失效
    用于在数据高速缓存单元中实现单个时钟周期线替换的方法和装置

    公开(公告)号：US5526510A

    公开(公告)日：1996-06-11

    申请号：US315889

    申请日：1994-09-30

    申请人： Haitham Akkary ,  Mandar S. Joshi ,  Rob Murray ,  Brent E. Lince ,  Paul D. Madland ,  Andrew F. Glew ,  Glenn J. Hinton

    发明人： Haitham Akkary ,  Mandar S. Joshi ,  Rob Murray ,  Brent E. Lince ,  Paul D. Madland ,  Andrew F. Glew ,  Glenn J. Hinton

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F12/0859

    摘要： The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.

    摘要翻译： 数据高速缓存单元包括单独的填充缓冲器和单独的回写缓冲器。 填充缓冲器存储用于转移到数据高速缓存单元的数据高速缓存组中的一个或多个高速缓存行。 回写缓冲器在回写到主存储器之前存储从数据高速缓冲存储器中逐出的单个高速缓存行。 提供电路用于将高速缓存行从填充缓冲器传送到数据高速缓存组，同时将受害缓存行从数据高速缓冲存储体传输到回写缓冲器。 这样允许整个替换操作仅在单个时钟周期中执行。 在特定实现中，在能够对存储器指令进行推测和无序处理的微处理器中采用数据高速缓存单元。 此外，微处理器并入多处理器计算机系统中，其中每个微处理器能够窥探每个其他微处理器的数据高速缓存单元的高速缓存行。 数据高速缓存单元也是非阻塞缓存。

    Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store
    45.
    发明授权
    Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store 失效
    用于防止对依赖于已经存储的商店的自修改代码序列的指令的不正确取出的方法和装置

    公开(公告)号：US5434987A

    公开(公告)日：1995-07-18

    申请号：US350379

    申请日：1994-12-05

    申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

    发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3812

    摘要： A number of identical matching circuits are integrated into the store address buffer, one matching circuit to each buffer slot, for generating a number of match signals, one for each detected match, using at most the entire source address of an instruction being fetched and the corresponding portions of the store destination addresses of the buffered store instructions. Additionally, a stall signal generator complimentary to the store address buffer is provided for generating a single stall signal for the bus controller, using the match signals, thereby stalling an instruction fetch from a source address that is potentially a store destination of one of the buffered store instructions with minimal performance cost.

    摘要翻译： 将多个相同的匹配电路集成到存储地址缓冲器中，每个缓冲器时隙具有一个匹配电路，用于生成多个匹配信号，每个检测到的匹配一个，最多使用正在读取的指令的整个源地址， 缓存存储指令的存储目标地址的对应部分。 此外，提供与存储地址缓冲器相互补充的失速信号发生器，用于使用匹配信号产生用于总线控制器的单个停止信号，从而阻止来自潜在地存储缓冲器之一的存储目的地的源地址的指令获取 存储指令，性能成本最低。

    Method and apparatus for processing memory-type information within a microprocessor
    48.
    发明授权
    Method and apparatus for processing memory-type information within a microprocessor 失效
    用于处理微处理器内的存储器类型信息的方法和装置

    公开(公告)号：US5751996A

    公开(公告)日：1998-05-12

    申请号：US767799

    申请日：1996-12-17

    申请人： Andrew F. Glew ,  Glenn J. Hinton

    发明人： Andrew F. Glew ,  Glenn J. Hinton

    IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/30043 ,  G06F12/0804 ,  G06F12/0888 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857

    摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. For example, if the memory location identified by the micro-instruction is known to be uncacheable, a data cache unit is bypassed and external memory is accessed directly. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor capable of generating speculative memory micro-instruction. Also, the microprocessor may be only one of a number of microprocessors within a multiprocessor system.

    摘要翻译： 识别包含有存储器位置范围的存储器类型的存储器类型值被明确地存储在微处理器内。 在处理诸如加载或存储之类的存储器微指令之前，为由存储器微指令识别的存储器位置确定存储器类型。 一旦已知存储器类型，存储器微指令根据多种处理协议中的任何一种被处理，包括直写处理，回写处理，写保护处理，限制高速缓存处理，不可缓存的可写入写入 - 组合处理或不可缓解的处理。 通过在微处理器内显式提供存储器类型信息，在微指令被处理之前，已经知道由微指令识别的存储器类型。 因此，处理微指令的协议可以有效地针对存储器类型进行定制。 例如，如果由微指令识别的存储器位置已知是不可缓存的，则旁路数据高速缓存单元，并直接访问外部存储器。 在示例性实施例中，微处理器是能够产生推测存储器微指令的无序微处理器。 此外，微处理器可能只是多处理器系统内的多个微处理器之一。

    Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
    49.
    发明授权
    Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers 失效
    使用多个填充缓冲器以非阻塞方式高速缓存数据的方法和装置

    公开(公告)号：US5671444A

    公开(公告)日：1997-09-23

    申请号：US731545

    申请日：1996-10-15

    申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0859 ,  G06F12/0831

    摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

    摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

    Apparatus and method for renaming registers in a processor and resolving data dependencies thereof
    50.
    发明授权
    Apparatus and method for renaming registers in a processor and resolving data dependencies thereof 失效
    用于在处理器中重命名寄存器并解决其数据依赖性的装置和方法

    公开(公告)号：US5524262A

    公开(公告)日：1996-06-04

    申请号：US443189

    申请日：1995-05-17

    申请人： Robert P. Colwell ,  Andrew F. Glew

    发明人： Robert P. Colwell ,  Andrew F. Glew

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3828 ,  G06F9/30112 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： A bypass mechanism within a register alias table unit (RAT) for handling source-destination dependencies between operands of a given set of operations issued simultaneously within a superscalar microproessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register. In general the RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies that reduce overall superscalar processing performance for the microprocessor. The bypass mechanism of the present invention handles both floating point and integer registers and, in addition, a second bypass mechanism is included in the RAT priority write operation.

    摘要翻译： 寄存器别名表单元（RAT）内的旁路机制，用于处理在超标量微处理器内同时发出的给定操作集的操作数之间的源 - 目的地依赖关系。 给定集合的操作以程序顺序呈现，并且当特定操作的源寄存器也用作给定操作集合中的先前操作的目标寄存器时，发生数据依赖性。 在这种情况下，RAT单元的初始读取将不会提供源寄存器的最新的重命名。 本发明包括用于检测该状况的比较机构。 还包括旁路机构，用于通过用分配给具有匹配的物理目的地寄存器的先前操作的最近分配的物理目的地寄存器来初始读取RAT单元旁路物理源寄存器输出。 通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除虚假数据依赖性，从而减少整体 微处理器的超标量处理性能。 本发明的旁路机构处理浮点和整数寄存器，并且另外在RAT优先级写入操作中包括第二旁路机制。