公开(公告)号：US07028166B2

公开(公告)日：2006-04-11

申请号：US10135496

申请日：2002-04-30

申请人： James K. Pickett

发明人： James K. Pickett

IPC分类号： G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/383 ,  G06F9/3842

摘要： A system may include a memory file, which includes an entry configured to store a first addressing pattern and a first tag, and an execution core coupled to the memory file. The memory file may be configured to compare the first addressing pattern included in the entry to a second addressing pattern of a load operation. If the second addressing pattern matches the first addressing pattern stored in the entry, the memory file is configured to link a data value identified by the first tag to a speculative result of the load operation. The execution core is configured to access the speculative result when executing a second operation that is dependent on the load operation.

摘要翻译： 系统可以包括存储器文件，其包括被配置为存储第一寻址模式和第一标签的条目以及耦合到存储器文件的执行核心。 存储器文件可以被配置为将包括在条目中的第一寻址模式与加载操作的第二寻址模式进行比较。 如果第二寻址模式与存储在条目中的第一寻址模式匹配，则存储器文件被配置为将由第一标签识别的数据值链接到加载操作的推测结果。 执行核心被配置为在执行取决于加载操作的第二操作时访问推测结果。

公开(公告)号：US06944744B2

公开(公告)日：2005-09-13

申请号：US10228929

申请日：2002-08-27

申请人： Ashraf Ahmed ,  Michael A. Filippo ,  James K. Pickett

发明人： Ashraf Ahmed ,  Michael A. Filippo ,  James K. Pickett

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3885

摘要： A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may be scheduled to execute an instruction as a single double-wide execution unit or as two independently schedulable single-wide execution units. Functional unit portions may be independently schedulable for execution of instructions operating on a first data type (e.g. SISD instructions). For single-wide instructions, functional unit portions may be scheduled independently. An issue lock mechanism may lock functional unit portions together so that they form a single multi-wide functional unit. For certain multi-wide instructions (e.g. certain SIMD instructions), an instruction operating on a multi-wide or vector data type may be scheduled so that the full multi-wide operation is performed concurrently by functional unit portions locked together as a one wide functional unit.

摘要翻译： 处理器的功能单元可以被配置为作为单个，宽功能单元或多个独立的较窄单元的指令进行操作。 例如，可以将执行单元调度为执行作为单个双宽执行单元的指令或作为两个可独立调度的单宽执行单元执行。 功能单元部分可以是独立可调度的，用于执行基于第一数据类型（例如SISD指令）的指令。 对于单宽指令，可以独立地调度功能单元部分。 问题锁定机构可以将功能单元部分锁定在一起，使得它们形成单个多宽度功能单元。 对于某些多宽指令（例如某些SIMD指令），可以调度在多宽或向量数据类型上操作的指令，使得全功能多操作由作为一个宽功能的锁定在一起的功能单元部分同时执行 单元。

公开(公告)号：US06845442B1

公开(公告)日：2005-01-18

申请号：US10135497

申请日：2002-04-30

申请人： Kevin Michael Lepak ,  Benjamin Thomas Sander ,  James K. Pickett

发明人： Kevin Michael Lepak ,  Benjamin Thomas Sander ,  James K. Pickett

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3842

摘要： A system may include a scheduler and an execution core. The scheduler includes an entry allocated to an operation. The entry includes a non-speculative tag and a speculative tag, and both the non-speculative tag and the speculative tag are associated with a first operand of the operation. The scheduler is configured to issue the operation in response to a data value identified by the speculative tag being available. The execution core may be configured to execute the operation using the data value identified by the speculative tag. The scheduler may be configured to reissue the operation if the non-speculative tag appears on a result bus.

摘要翻译： 系统可以包括调度器和执行核心。 调度器包括分配给操作的条目。 条目包括非推测标签和推测标签，非推测标签和推测标签都与操作的第一个操作数相关联。 调度器被配置为响应于由可推测标签识别的数据值发出操作。 执行核心可以被配置为使用由推测标签识别的数据值来执行操作。 如果非推测标签出现在结果总线上，则调度器可以被配置为重新发出操作。

公开(公告)号：US06175908B1

公开(公告)日：2001-01-16

申请号：US09070392

申请日：1998-04-30

申请人： James K. Pickett

发明人： James K. Pickett

IPC分类号： G06F9312

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816

摘要： A superscalar microprocesor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their storage within an instruction cache. In one system, a predecode unit is configured to generate a plurality of predecode bits including a start bit, an end bit, and a functional bit for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions to a plurality of decode units within the superscalar microprocessor. The predecode unit is configured such that the meaning of the functional bit of a particular predecode tag is dependent upon the status of the start bit. The predecode unit is further configured to generate a functional bit associated with each byte of an instruction other than the starting byte, which indicate whether the associated byte is a prefix or opcode. The encoding of the predecode tags is such that a relatively large amount of predecode information may be conveyed with a relatively small number of predecode bits.

摘要翻译： 提供了一种超标量微处理器，其包括适于预编码可变字节长度指令的预解码单元。 预解码单元在指令存储之前对指令进行预解码。 在一个系统中，预解码单元被配置为生成包括每个指令字节的起始位，结束位和功能位的多个预解码位。 与每个指令字节相关联的多个预解码位被统称为预解码标签。 指令对准单元然后使用预解码标签将可变字节长度指令分派给超标量微处理器内的多个解码单元。 预解码单元被配置为使得特定预解码标签的功能位的含义取决于起始位的状态。 预解码单元还被配置为生成与起始字节以外的指令的每个字节相关联的功能位，其指示相关联的字节是前缀还是操作码。 预解码标签的编码使得可以以相对较少数量的预解码比特传送相对大量的预解码信息。

公开(公告)号：US06073230A

公开(公告)日：2000-06-06

申请号：US873113

申请日：1997-06-11

申请人： James K. Pickett ,  Thang M. Tran

发明人： James K. Pickett ,  Thang M. Tran

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3806 ,  G06F12/0864 ,  G06F9/3814 ,  G06F2212/6082

摘要： An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a first group of contiguous instruction bytes within the instruction cache, as well as a corresponding branch prediction block. The branch prediction block is stored in a branch prediction storage, and includes a predicted sequential way value. The control unit is further configured to convey a second index and a second way to the instruction cache in a second clock cycle succeeding the first clock cycle. This second index and second way select a second group of contiguous instruction bytes from the instruction cache. The second way is selected to be the predicted sequential way value stored in the branch prediction block corresponding to the first group of contiguous instruction bytes in response to a branch prediction algorithm employed by the control unit predicting a sequential execution path. Advantageously, a set associative instruction cache utilizing this method of way prediction may operate at higher frequencies (i.e., lower clock cycles) than if tag comparison were used to select the correct way.

摘要翻译： 采用顺序方式预测的指令提取单元。 指令提取单元包括控制单元，其被配置为在第一时钟周期中将第一索引和第一路径传送到指令高速缓存。 第一索引和第一方式选择指令高速缓存内的第一组连续指令字节，以及相应的分支预测块。 分支预测块存储在分支预测存储器中，并且包括预测的顺序路径值。 控制单元还被配置为在第一时钟周期之后的第二时钟周期中将第二索引和第二路径传送到指令高速缓存。 该第二索引和第二方式从指令高速缓存中选择第二组连续的指令字节。 响应于预测顺序执行路径的控制单元使用的分支预测算法，第二种方式被选择为存储在与第一组连续指令字节对应的分支预测块中的预测顺序方式值。 有利地，使用这种方式预测方法的集合关联指令高速缓存可以比使用标签比较来选择正确的方式更高的频率（即，较低的时钟周期）操作。

公开(公告)号：US5940876A

公开(公告)日：1999-08-17

申请号：US831195

申请日：1997-04-02

申请人： James K. Pickett

发明人： James K. Pickett

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/345 ,  G06F9/32

CPC分类号： G06F9/30043 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/30185 ,  G06F9/345 ,  G06F9/3455

摘要： A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

公开(公告)号：US5933626A

公开(公告)日：1999-08-03

申请号：US874030

申请日：1997-06-12

申请人： Rupaka Mahalingaiah ,  James K. Pickett

发明人： Rupaka Mahalingaiah ,  James K. Pickett

IPC分类号： G06F11/34 ,  G06F11/36 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3466 ,  G06F11/3648 ,  G06F11/348

摘要： A microprocessor implements an instruction tracing mechanism that saves the state of the microprocessor without special hardware. Prior to the execution of a traced instruction, a trace microcode routine is implemented that saves the state of the microprocessor to external memory. The state information saved by the trace microcode routine varies depending upon the amount of data needed by the end user. After the state of the processor has been saved, the trace instruction is executed. State information that changed during the execution of the trace instruction is saved to memory prior to a subsequent instruction. The trace instruction mechanism advantageously requires minimal special hardware and expedites the saving of the processor state information.

公开(公告)号：US5764946A

公开(公告)日：1998-06-09

申请号：US826884

申请日：1997-04-08

申请人： Thang M. Tran ,  James K. Pickett

发明人： Thang M. Tran ,  James K. Pickett

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F9/3885 ,  G06F12/0864 ,  G06F9/3832 ,  G06F9/3844 ,  G06F2212/6082

摘要： A superscalar microprocessor is provided employing a way prediction unit which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The microprocessor may achieve high frequency operation while using an associative instruction cache. An instruction fetch can be made every clock cycle using the predicted fetch address from the way prediction unit until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.

摘要翻译： 提供超标量微处理器，其使用预测下一个提取地址的方式预测单元以及当前提取地址所在的指令高速缓存的方式，同时从指令高速缓存读取与当前提取相关联的指令。 微处理器可以在使用关联指令高速缓存时实现高频操作。 每个时钟周期可以使用来自方式预测单元的预测提取地址进行指令提取，直到预测到不正确的下一个提取地址或错误的方式。 来自预测方式的指令被提供给超标量微处理器每个时钟周期的指令处理流水线。

公开(公告)号：US5339395A

公开(公告)日：1994-08-16

申请号：US947126

申请日：1992-09-17

申请人： James K. Pickett ,  Philip A. Inman ,  Matthew D. Sale

发明人： James K. Pickett ,  Philip A. Inman ,  Matthew D. Sale

IPC分类号： G06F13/38 ,  G06F13/14

CPC分类号： G06F13/385

摘要： An interface circuit is described for interfacing a peripheral device and a microprocessor to enable data transference between a memory location within the peripheral device and a data bus of the microprocessor. In accordance with the type of bus control used by the microprocessor, the interface circuit is operated in either a synchronous mode or an asynchronous mode. The interface includes a state machine that responds to the mode of interface operation, a clock signal provided by the microprocessor, requests from the microprocessor to access an addressed peripheral memory location, and a busy signal from the peripheral device indicating when the peripheral is engaged in transferring data between the interface circuit and an addressed peripheral memory location. Preferably, the interface also operates to detect error conditions based on changes in the access request during data transference between the microprocessor and the peripheral device. In response to detecting an error condition, the state machine acts to interrupt data transference to avoid the transfer of invalid data.

摘要翻译： 描述了用于将外围设备和微处理器连接以实现外围设备内的存储器位置与微处理器的数据总线之间的数据传输的接口电路。 根据微处理器使用的总线控制类型，接口电路以同步模式或异步模式工作。 该接口包括响应于接口操作模式的状态机，由微处理器提供的时钟信号，来自微处理器的请求以访问寻址的外围存储器位置，以及来自外围设备的忙信号，指示外围设备何时进入 在接口电路和寻址的外围存储器位置之间传送数据。 优选地，接口还用于基于微处理器和外围设备之间的数据传输期间的访问请求的变化来检测错误状况。 响应于检测到错误状况，状态机用于中断数据传输，以避免传输无效数据。

公开(公告)号：US4755696A

公开(公告)日：1988-07-05

申请号：US66319

申请日：1987-06-25

申请人： James K. Pickett

发明人： James K. Pickett

IPC分类号： G01R19/00 ,  H03K5/24

CPC分类号： G01R19/0038

摘要： A binary threshold comparator is disclosed for first and second binary numbers, wherein the first is variable and the second is a threshold or reference, with the complement of the second number available. The comparator may be a high threshold (greater/equal) comparator or a low threshold (less/equal) comparator. It comprises 5 MOSFETs per bit stage, with two additional MOSFETs per comparator for high/low determination and carry in precharge. A particular multi-bit embodiment of the comparator has a modified most significant bit stage which provides a complement of the normal output when the most significant bits of the numbers to be compared are different to prevent an immediate reversal of comparator output when a counter containing the variable number rolls over from all ones to all zeros or vice versa.

摘要翻译： 公开了用于第一和第二二进制数的二进制阈值比较器，其中第一个是可变的，第二个是二进制阈值比较器，其中第二个是可变的，第二个是阈值或参考。 比较器可以是高阈值（大/等）比较器或低阈值（较小/等于）比较器。 它每个位阶段包括5个MOSFET，每个比较器有两个额外的MOSFET用于高/低确定，并进行预充电。 比较器的特定多位实施例具有经修改的最高有效位级，当要比较的数目的最高有效位不同时，提供正常输出的补码，以防止当包含比较器的计数器时立即反转比较器输出 可变数量从所有数字翻转到全零，反之亦然。