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1.发明授权Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches 失效指令提取单元被配置为为顺序指令提取提供顺序方式预测
公开(公告)号：US06073230A
公开(公告)日：2000-06-06
申请号：US873113
申请日：1997-06-11
申请人： James K. Pickett , Thang M. Tran
发明人： James K. Pickett , Thang M. Tran
CPC分类号： G06F9/3806 , G06F12/0864 , G06F9/3814 , G06F2212/6082
摘要： An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a first group of contiguous instruction bytes within the instruction cache, as well as a corresponding branch prediction block. The branch prediction block is stored in a branch prediction storage, and includes a predicted sequential way value. The control unit is further configured to convey a second index and a second way to the instruction cache in a second clock cycle succeeding the first clock cycle. This second index and second way select a second group of contiguous instruction bytes from the instruction cache. The second way is selected to be the predicted sequential way value stored in the branch prediction block corresponding to the first group of contiguous instruction bytes in response to a branch prediction algorithm employed by the control unit predicting a sequential execution path. Advantageously, a set associative instruction cache utilizing this method of way prediction may operate at higher frequencies (i.e., lower clock cycles) than if tag comparison were used to select the correct way.
摘要翻译： 采用顺序方式预测的指令提取单元。 指令提取单元包括控制单元，其被配置为在第一时钟周期中将第一索引和第一路径传送到指令高速缓存。 第一索引和第一方式选择指令高速缓存内的第一组连续指令字节，以及相应的分支预测块。 分支预测块存储在分支预测存储器中，并且包括预测的顺序路径值。 控制单元还被配置为在第一时钟周期之后的第二时钟周期中将第二索引和第二路径传送到指令高速缓存。 该第二索引和第二方式从指令高速缓存中选择第二组连续的指令字节。 响应于预测顺序执行路径的控制单元使用的分支预测算法，第二种方式被选择为存储在与第一组连续指令字节对应的分支预测块中的预测顺序方式值。 有利地，使用这种方式预测方法的集合关联指令高速缓存可以比使用标签比较来选择正确的方式更高的频率（即，较低的时钟周期）操作。
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2.发明授权Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address 失效超标量微处理器采用方式预测单元来预测指令获取地址的方式并且同时提供对应于获取地址的分支预测地址
公开(公告)号：US5764946A
公开(公告)日：1998-06-09
申请号：US826884
申请日：1997-04-08
申请人： Thang M. Tran , James K. Pickett
发明人： Thang M. Tran , James K. Pickett
CPC分类号： G06F9/3885 , G06F12/0864 , G06F9/3832 , G06F9/3844 , G06F2212/6082
摘要： A superscalar microprocessor is provided employing a way prediction unit which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The microprocessor may achieve high frequency operation while using an associative instruction cache. An instruction fetch can be made every clock cycle using the predicted fetch address from the way prediction unit until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.
摘要翻译： 提供超标量微处理器，其使用预测下一个提取地址的方式预测单元以及当前提取地址所在的指令高速缓存的方式，同时从指令高速缓存读取与当前提取相关联的指令。 微处理器可以在使用关联指令高速缓存时实现高频操作。 每个时钟周期可以使用来自方式预测单元的预测提取地址进行指令提取，直到预测到不正确的下一个提取地址或错误的方式。 来自预测方式的指令被提供给超标量微处理器每个时钟周期的指令处理流水线。
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3.发明授权Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register 失效用于存储推测寄存器状态的推测寄存器文件，以及消除使用寄存器的指令之间的依赖关系
公开(公告)号：US5892936A
公开(公告)日：1999-04-06
申请号：US879520
申请日：1997-06-20
CPC分类号： G06F9/3812 , G06F9/30101 , G06F9/30152 , G06F9/3016 , G06F9/3816 , G06F9/382 , G06F9/3824 , G06F9/3828 , G06F9/3832 , G06F9/3842
摘要： A superscalar microprocessor configured to speculatively generate register values associated with a particular register is provided. Multiple register values are generated in parallel, wherein each speculatively generated register value accounts for modifications of the register value by each of the instructions prior to the instruction for which the register value is generated. Instructions which are dependent upon each other for the register values thus generated may be executed concurrently. In one specific embodiment, the present microprocessor generates register values for the ESP register. The speculatively generated register value resulting from the modifications performed by the instructions decoded during a clock cycle is stored in a speculative register file along with constants used to generate the register value associated with each individual instruction. When a mispredicted branch instruction is detected, the register value generated during the decode of the mispredicted branch instruction may be adjusted using the stored constants. The adjustment performed reflects the value of the register at the execution of the mispredicted branch instruction.
摘要翻译： 提供了配置成推测性地生成与特定寄存器相关联的寄存器值的超标量微处理器。 并行产生多个寄存器值，其中每个推测产生的寄存器值在生成寄存器值的指令之前考虑每个指令对寄存器值的修改。 对于由此生成的寄存器值彼此依赖的指令可以同时执行。 在一个具体实施例中，本微处理器产生ESP寄存器的寄存器值。 由在时钟周期期间解码的指令执行的修改产生的推测产生的寄存器值与用于生成与每个单独指令相关联的寄存器值的常数一起存储在推测寄存器文件中。 当检测到错误预测的分支指令时，可以使用存储的常数来调整在误预测分支指令的解码期间生成的寄存器值。 执行的调整反映了在执行错误预测的分支指令时寄存器的值。
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4.发明授权Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array 失效数据存储单元和通过预览标签阵列在一个时钟周期内将数据存储到可锁定缓存中的方法
公开(公告)号：US5761712A
公开(公告)日：1998-06-02
申请号：US850290
申请日：1997-05-05
申请人： Thang M. Tran , James K. Pickett
发明人： Thang M. Tran , James K. Pickett
CPC分类号： G06F9/52 , G06F12/126 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： A data memory unit having a load/store unit and a data cache is provided which allows store instructions that are part of a load-op-store instruction to be executed with one access to a data cache. The load/store unit is configured with a load/store buffer having a checked bit and a way field for each buffer storage location. For load-op-store instructions, the checked bit associated with the store portion of the of the instruction is set when the load portion of the instruction accesses and hits the data cache. Also, the way field associated with the store portion is set to the way of the data cache in which the load portion hits. The data cache is configured with a locking mechanism for each cache line stored in the data cache. When the load portion of a load-op-store instruction is executed, the associated line is locked such that the line will remain in the data cache until a store instruction executes. In this way, the store portion of the load-op-store instruction is guaranteed to hit the data cache. The store may then store its data into the data cache without first performing a read cycle to determine if the store address hits the data cache.
摘要翻译： 提供具有加载/存储单元和数据高速缓存的数据存储单元，其允许作为加载操作存储指令的一部分的存储指令通过对数据高速缓存的一次访问来执行。 加载/存储单元配置有具有每个缓冲存储位置的检查位和方式字段的加载/存储缓冲器。 对于加载操作存储指令，当指令的加载部分访问并且命中数据高速缓冲存储器时，设置与指令的存储部分相关联的检查位。 此外，与存储部分相关联的方式字段被设置为加载部分命中的数据高速缓存的方式。 数据高速缓存配置有存储在数据高速缓存中的每个高速缓存行的锁定机制。 当执行加载操作存储指令的加载部分时，相关联的行被锁定，使得行将保留在数据高速缓存中直到存储指令执行。 以这种方式，加载操作存储指令的存储部分被保证命中数据高速缓存。 然后，存储器可以将其数据存储到数据高速缓存中，而不首先执行读取周期以确定存储地址是否触发数据高速缓存。
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5.发明授权Fetching instructions from an instruction cache using sequential way prediction 有权使用顺序方式预测从指令高速缓存中获取指令
公开(公告)号：US6101595A
公开(公告)日：2000-08-08
申请号：US246270
申请日：1999-02-08
申请人： James K. Pickett , Thang M. Tran
发明人： James K. Pickett , Thang M. Tran
CPC分类号： G06F9/3806 , G06F12/0864 , G06F9/3814 , G06F2212/6082
摘要： An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a first group of contiguous instruction bytes within the instruction cache, as well as a corresponding branch prediction block. The branch prediction block is stored in a branch prediction storage, and includes a predicted sequential way value. The control unit is further configured to convey a second index and a second way to the instruction cache in a second clock cycle succeeding the first clock cycle. This second index and second way select a second group of contiguous instruction bytes from the instruction cache. The second way is selected to be the predicted sequential way value stored in the branch prediction block corresponding to the first group of contiguous instruction bytes in response to a branch prediction algorithm employed by the control unit predicting a sequential execution path. Advantageously, a set associative instruction cache utilizing this method of way prediction may operate at higher frequencies (i.e., lower clock cycles) than if tag comparison were used to select the correct way.
摘要翻译： 采用顺序方式预测的指令提取单元。 指令提取单元包括控制单元，其被配置为在第一时钟周期中将第一索引和第一路径传送到指令高速缓存。 第一索引和第一方式选择指令高速缓存内的第一组连续指令字节，以及相应的分支预测块。 分支预测块存储在分支预测存储器中，并且包括预测的顺序路径值。 控制单元还被配置为在第一时钟周期之后的第二时钟周期中将第二索引和第二路径传送到指令高速缓存。 该第二索引和第二方式从指令高速缓存中选择第二组连续的指令字节。 响应于预测顺序执行路径的控制单元使用的分支预测算法，第二种方式被选择为存储在与第一组连续指令字节对应的分支预测块中的预测顺序方式值。 有利地，使用这种方式预测方法的集合关联指令高速缓存可以比使用标签比较来选择正确的方式更高的频率（即，较低的时钟周期）操作。
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公开(公告)号：US5872943A
公开(公告)日：1999-02-16
申请号：US690382
申请日：1996-07-26
申请人： James K. Pickett , Thang M. Tran
发明人： James K. Pickett , Thang M. Tran
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3822
摘要： A predecode unit within a microprocessor predecodes a cache line of instruction bytes for storage within the instruction cache of the microprocessor. The predecode unit produces multiple shift amounts, each of which identify the beginning of a particular instruction within the instruction cache line. The shift amounts are stored in the instruction cache with the instruction bytes, and are conveyed when the instruction bytes are fetched for execution by the microprocessor. An instruction alignment unit decodes the shift amounts to locate instructions within the fetched instruction bytes. Each shift amount directly identifies a corresponding instruction for dispatch, and therefore decoding the shift amount directly results in controls for shifting the instruction bytes such that the identified instruction is conveyed to a corresponding issue position. The number of shift amounts stored may be equal to the number of issue positions within the microprocessor. The instruction alignment unit scans the start and end byte predecode data (which is also provided by the predecode unit and stored in the instruction cache) to detect any additional instructions within the cache line (e.g. instructions not identified by the shift amounts). Additional shift amounts are generated and used by the instruction alignment unit to dispatch instructions during subsequent clock cycles.
摘要翻译： 微处理器中的预解码单元预先对指令字节的高速缓存行进行存储，以存储在微处理器的指令高速缓存内。 预解码单元产生多个移位量，每个移位量标识指令高速缓存行内特定指令的开始。 移位量存储在具有指令字节的指令高速缓存中，并且当指令字节被提取以由微处理器执行时被传送。 指令对准单元对移位量进行解码，以定位取出的指令字节内的指令。 每个移位量直接识别用于调度的相应指令，因此解码移位量直接导致用于移位指令字节的控制，使得所识别的指令被传送到相应的发行位置。 存储的移位量的数量可以等于微处理器内的发放位置的数目。 指令对准单元扫描开始和结束字节预解码数据（其也由预解码单元提供并存储在指令高速缓存中）以检测高速缓存行内的任何附加指令（例如，未被移位量标识的指令）。 附加移位量由指令对准单元产生并用于在随后的时钟周期期间调度指令。
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公开(公告)号：US5848433A
公开(公告)日：1998-12-08
申请号：US838680
申请日：1997-04-09
申请人： Thang M. Tran , James K. Pickett
发明人： Thang M. Tran , James K. Pickett
CPC分类号： G06F9/3806 , G06F12/0864 , G06F9/3832 , G06F2212/6082
摘要： A way prediction unit for a superscalar microprocessor is provided which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The way prediction unit is intended for high frequency microprocessors in which associative caches tend to be clock cycle limiting, causing the instruction fetch mechanism to require more than one clock cycle between fetch requests. Therefore, an instruction fetch can be made every clock cycle using the predicted fetch address until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.
摘要翻译： 提供了一种用于超标量微处理器的方式预测单元，其预测下一个提取地址以及当前提取地址所在的指令高速缓存的方式，同时从指令高速缓存读取与当前提取相关联的指令。 预测单元用于高频微处理器的方式，其中关联高速缓存趋向于是时钟周期限制，导致指令获取机制在提取请求之间需要多于一个时钟周期。 因此，可以使用预测的提取地址进行每个时钟周期的指令提取，直到预测到不正确的下一个提取地址或错误的方式。 来自预测方式的指令被提供给超标量微处理器每个时钟周期的指令处理流水线。
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8.发明授权Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction 失效用于存储对应于由多个并行记录指令更新的寄存器的推测结果的推测寄存器存储器
公开(公告)号：US5933618A
公开(公告)日：1999-08-03
申请号：US550218
申请日：1995-10-30
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0846 , G06F12/0864 , G06F9/30054 , G06F9/30152 , G06F9/3806 , G06F9/3814 , G06F9/3832 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： A microprocessor including a reorder buffer configured to store speculative register values regarding a particular register is provided. One value is stored for each set of concurrently decoded instructions which are outstanding within the microprocessor, reflecting the updates of each instruction within the set which updates the register. Additionally, the reorder buffer stores a set of constants indicative of the modification of the register by each instruction within the set of concurrently decoded instructions. Recovery from a mispredicted branch instruction (or from an instruction which causes an exception, a TRAP instruction, or an interrupt) may be achieved by utilizing the constants to adjust the result generated for the set of concurrently decoded instructions including the mispredicted branch instruction. The constants generated to indicate the modifications of the particular register may additionally allow multiple instructions having a dependency for the particular register to execute in parallel.
摘要翻译： 提供了一种微处理器，其包括配置为存储关于特定寄存器的推测寄存器值的重排序缓冲器。 对于在微处理器内未完成的每组并行解码的指令存储一个值，反映了更新寄存器的集合内的每个指令的更新。 此外，重排序缓冲器存储指示该并发解码指令集内的每个指令对寄存器进行修改的一组常数。 可以通过利用常数来调整针对包括错误预测的分支指令的并行解码指令集合生成的结果来实现从错误预测的分支指令（或来自导致异常，TRAP指令或中断的指令）的恢复。 为了指示特定寄存器的修改产生的常数可另外允许具有对特定寄存器的依赖性的多个指令并行执行。
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9.发明授权Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations 失效超标量微处理器加载/存储单元采用统一的缓冲区和单独的指针进行加载和存储操作
公开(公告)号：US5832297A
公开(公告)日：1998-11-03
申请号：US968308
申请日：1997-11-12
申请人： H. S. Ramagopal , Thang M. Tran , James K. Pickett
发明人： H. S. Ramagopal , Thang M. Tran , James K. Pickett
CPC分类号： G06F9/30087 , G06F9/30047 , G06F9/3005 , G06F9/30152 , G06F9/3806 , G06F9/3816 , G06F9/382 , G06F9/3824 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3855
摘要： A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Because each storage location may contain either a load or a store memory operation, the number of available storage locations for load memory operations is maximally the number of storage locations in the entire buffer. Similarly, the number of available storage locations for store memory operations is maximally the number of storage locations in the entire buffer. This invention improves use of silicon area for load and store buffers by implementing, in a smaller area, a performance-equivalent alternative to the separate load and store buffer approach previously used in many superscalar microprocessors.
摘要翻译： 提供了一个加载/存储缓冲区，允许加载存储器操作和存储存储器操作存储在其中。 由于每个存储位置可以包含加载或存储存储器操作，所以用于加载存储器操作的可用存储位置的数量最大限度地为整个缓冲器中的存储位置的数量。 类似地，用于存储存储器操作的可用存储位置的数量最大限度地是整个缓冲器中的存储位置的数量。 本发明通过在较小的区域中实现与许多超标量微处理器中先前使用的单独的负载和存储缓冲器方法的性能等效的替代方案来改进硅面积用于负载和存储缓冲器的使用。
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公开(公告)号：US09547593B2
公开(公告)日：2017-01-17
申请号：US13036321
申请日：2011-02-28
申请人： Thang M. Tran
发明人： Thang M. Tran
CPC分类号： G06F12/0811 , G06F9/3851 , G06F12/0842 , G06F2212/601 , Y02D10/13
摘要： A microprocessor system is disclosed that includes a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode. A second data cache is shared by a second group of one or more program threads in the multi-thread mode and is used as a victim cache for the first data cache in the single-thread mode.
摘要翻译： 公开了一种微处理器系统，其包括由多线程模式中的一个或多个程序线程的第一组共享的第一数据高速缓存，并且由单线程模式中的一个程序线程使用。 第二数据高速缓存由多线程模式中的一个或多个程序线程的第二组共享，并且以单线程模式用作第一数据高速缓存的受害缓存。
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