公开(公告)号：US4769786A

公开(公告)日：1988-09-06

申请号：US885618

申请日：1986-07-15

申请人： Richard R. Garnache ,  Donald M. Kenney

发明人： Richard R. Garnache ,  Donald M. Kenney

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  G11C13/00 ,  G11C11/40

CPC分类号： H01L27/10841

摘要： A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

公开(公告)号：US4470191A

公开(公告)日：1984-09-11

申请号：US448125

申请日：1982-12-09

申请人： Peter E. Cottrell ,  Henry J. Geipel, Jr. ,  Donald M. Kenney

发明人： Peter E. Cottrell ,  Henry J. Geipel, Jr. ,  Donald M. Kenney

IPC分类号： H01L27/08 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L7/54 ,  B01J17/00 ,  H01L21/265

CPC分类号： H01L21/823878 ,  H01L21/76218 ,  Y10S438/975

摘要： A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

摘要翻译： 提供了一种制造平面CMOS结构的简单方法，其中首先形成体CMOS结构所需的隔离区域，N沟道器件场区域与半导体衬底中的N阱区域自对准，并且耐火材料被两次限定 形成P和N通道，第一定义屏蔽P沟道源极和漏极区域，同时定义N沟道，并且第二定义限定P沟道，同时使用光致抗蚀剂层掩蔽N沟道。 在该过程中，使用单个掩模级别的技术定义了阱区域并将必要的场掺杂自对准到阱区域以提供紧密间隔的N沟道和P沟道器件。

公开(公告)号：US4295924A

公开(公告)日：1981-10-20

申请号：US103981

申请日：1979-12-17

申请人： Richard R. Garnache ,  Donald M. Kenney

发明人： Richard R. Garnache ,  Donald M. Kenney

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/336 ,  H01L21/308

CPC分类号： H01L29/66621 ,  H01L21/30608

摘要： A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of V-groove devices, providing a conductive layer over the surface and then applying a layer of masking material over the conductive layer to form a planar upper surface, selectively etching the masking material until it remains only in the recesses and then selectively etching the exposed portion of the conductive layer.

摘要翻译： 一种用于在垂直集成的半导体器件中提供自对准导体的方法，其包括在用于制造V沟槽器件的半导体衬底的表面中提供凹槽，在表面上提供导电层，然后在该表面上施加一层掩模材料 导电层以形成平坦的上表面，选择性地蚀刻掩蔽材料，直到其仅保留在凹部中，然后选择性地蚀刻导电层的暴露部分。