利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.021 秒)

    Angle defined trench conductor for a semiconductor device
    1.
    发明授权
    Angle defined trench conductor for a semiconductor device 失效
    用于半导体器件的角度定义的沟槽导体

    公开(公告)号：US5610441A

    公开(公告)日：1997-03-11

    申请号：US444465

    申请日：1995-05-19

    申请人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son V. Nguyen

    发明人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son V. Nguyen

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/18 ,  H01L23/52

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  Y10S148/05

    摘要： Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon using strap that electrically connects the side wall with the polysilicon. Strap is sized such that it does not extend to the opposite side wall of trench, thereby avoiding short circuits. Having the polysilicon approximate the shadow line of the etch permits narrowing the distance between adjacent straps and in an array without the risk of creating a short.

    摘要翻译： 在沟槽中蚀刻多晶硅以在沟槽内产生导体，该导体具有接近最接近光束源的沟槽侧壁阴影的形状特征。 具体地，当第一侧壁最靠近光束源并且第二侧壁距离光束源最远时，第一侧壁上的多晶硅几乎与第一侧壁一样高，而在较大曝光侧的多晶硅 壁比第一侧壁大得多，并且近似于相对于梁的第二侧壁上的第一侧壁的阴影。 沟槽中的多晶硅可以是接近从侧壁顶部到侧壁上的阴影线的阴影线的实心角形块的形状，然而，优选地，多晶硅在沟槽中具有保形层的形式 以蚀刻，使得多晶硅最终具有近似于阴影线的成角度“U”形。 使用将侧壁与多晶硅电连接的带子与多晶硅接触。 带的尺寸使得其不延伸到沟槽的相对侧壁，从而避免短路。 使多晶硅近似于蚀刻的阴影线允许在相邻带之间和阵列之间的距离变窄，而不会产生短路。

    Method of making diffused buried plate trench DRAM cell array
    4.
    发明授权
    Method of making diffused buried plate trench DRAM cell array 失效
    扩散掩埋板沟槽DRAM单元阵列的制作方法

    公开(公告)号：US5348905A

    公开(公告)日：1994-09-20

    申请号：US112406

    申请日：1993-08-26

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10829

    摘要： A high density substrate plate DRAM cell memory device and process are described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.

    摘要翻译： 描述了高密度衬底板DRAM单元存储器件和工艺，其中与深沟槽电容器相邻地形成掩埋板区域，使得DRAM转移FET的衬底区域可以与半导体衬底上的其它FET电隔离。 掩埋区域部分地通过从深沟槽的侧壁的外部向外扩散部分地形成，并且部分地由完全围绕DRAM阵列区域的N阱表面扩散部分形成。

    Two square memory cells
    5.
    再颁专利
    Two square memory cells 失效

    公开(公告)号：USRE33972E

    公开(公告)日：1992-06-23

    申请号：US606809

    申请日：1990-10-30

    申请人： Richard R. Garnache ,  Donald M. Kenney

    发明人： Richard R. Garnache ,  Donald M. Kenney

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841

    摘要： A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

    Two square memory cells having highly conductive word lines
    6.
    发明授权
    Two square memory cells having highly conductive word lines 失效
    具有高导电性字线的两个方形存储单元

    公开(公告)号：US5001525A

    公开(公告)日：1991-03-19

    申请号：US329130

    申请日：1989-03-27

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10841

    摘要： A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, a storage capacitor having a storage node disposed within a given sidewall of the trench, a switching device coupled to the storage capacitor and having an elongated current carrying element disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench and a control element disposed on the sidewall of the trench between the storage capacitor and the elongated current carrying element, and an electrically conductive line disposed on the major surface of the semiconductor substrate in a direction orthogonal to the longitudinal axis of the trench and in contact with the control element of the switching device. Furthermore, two complete memory cells are formed at each trench-word line intersection with one cell formed on each side of the trench at each intersection.

    Trench interconnect for CMOS diffusion regions
    7.
    发明授权
    Trench interconnect for CMOS diffusion regions 失效
    用于CMOS扩散区的沟槽互连

    公开(公告)号：US4939567A

    公开(公告)日：1990-07-03

    申请号：US303986

    申请日：1989-01-30

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

    CPC分类号： H01L27/0921 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903

    摘要： A sub-surface interconnection structure for coupling an n-type diffusion to a p-type diffusion. The structure is a conductor-filled trench disposed between the diffusion regions. The trench has a thin dielectric layer on its sidewalls and bottom. The conductor within the trench contacts the diffusion regions. Parasitic device formation between the diffusion regions is suppressed because the trench provides a parasitic gate that is shorted to the parasitic source regions (i.e., the coupled diffusion regions). Moreover, the trench provides an enlarged contact to the coupled diffusion regions for the subsequently-applied metal layer.

    摘要翻译： 用于将n型扩散耦合到p型扩散的子表面互连结构。 该结构是设置在扩散区之间的导体填充沟槽。 沟槽在其侧壁和底部具有薄的介电层。 沟槽内的导体与扩散区接触。 由于沟槽提供与寄生源极区域（即耦合的扩散区域）短路的寄生栅极，所以抑制了扩散区域之间的寄生器件形成。 此外，沟槽为随后施加的金属层提供与耦合的扩散区的放大接触。

    Dense dynamic memory cell structure and process
    9.
    发明授权
    Dense dynamic memory cell structure and process 失效
    密集的动态存储单元结构和过程

    公开(公告)号：US4511911A

    公开(公告)日：1985-04-16

    申请号：US286110

    申请日：1981-07-22

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

    CPC分类号： H01L21/76202 ,  H01L23/535 ,  H01L27/10805 ,  H01L2924/0002

    摘要： A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense line connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/sense line diffusion region.

    摘要翻译： 提供动态存储器，其具有具有改进结构的单元，并且通过改进的过程来实现，其基本上减小了连接到单元的位/感测线的电容。 电池具有一个场效应晶体管和存储节点，并且电池结构包括位于导电层或场屏蔽的一部分下方并且在晶体管的栅电极的一部分下面的厚绝缘段，同时在整个扩散 位/感测线的区域以及围绕位/感测线扩散区域的基本上整个耗尽区上方。

    Trench capacitor precharge structure and leakage shield
    10.
    发明授权
    Trench capacitor precharge structure and leakage shield 失效
    沟槽电容器预充电结构和漏电屏蔽

    公开(公告)号：US5684314A

    公开(公告)日：1997-11-04

    申请号：US617138

    申请日：1996-03-18

    申请人： Donald M. Kenney

    发明人： Donald M. Kenney

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/108

    摘要： An integrated structure is provided that includes a DRAM cell with a trench storage capacitor, and a corresponding storage node precharge circuit. The entire structure ideally requires only eight square features of area per memory bit. The structure also provides a partial leakage current shield for the DRAM storage node diffusion, thereby improving the data hold time. A graded impurity region around the storage node diffusion enhances the leakage shielding effect. The structure can be operated independently as a DRAM leakage shield if the precharge circuit is not needed. In that case, a junction diffusion in the structure can be eliminated and a leakage shielding effect is still achieved.

    摘要翻译： 提供了一种集成结构，其包括具有沟槽存储电容器的DRAM单元和相应的存储节点预充电电路。 整个结构理想地仅需要每个存储器位的八个方形特征的面积。 该结构还为DRAM存储节点扩散提供了部分泄漏电流屏蔽，从而提高了数据保持时间。 存储节点扩散周围的渐变杂质区域增强了漏电屏蔽效应。 如果不需要预充电电路，则该结构可以独立地作为DRAM漏电屏蔽来操作。 在这种情况下，可以消除结构中的结扩散，并且仍然实现泄漏屏蔽效果。