公开(公告)号：US09899500B2

公开(公告)日：2018-02-20

申请号：US14269825

申请日：2014-05-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/872 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

公开(公告)号：US09099487B2

公开(公告)日：2015-08-04

申请号：US14098194

申请日：2013-12-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/861 ,  H01L31/107 ,  H01L29/66 ,  H01L29/866

CPC分类号： H01L29/866 ,  H01L21/76224 ,  H01L29/0611 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/66106

摘要： Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

摘要翻译： 提供齐纳二极管结构及相关制造方法和半导体器件。 示例性半导体器件包括第一和第二齐纳二极管结构。 第一齐纳二极管结构包括第一区域，与第一区域相邻的第二区域，以及与第一区域和第二区域相邻的第三区域，以提供被配置为影响第一区域的第一反向击穿电压 第一区域和第二区域之间的连接处。 第二齐纳二极管结构包括第四区域，与第四区域相邻的第五区域以及与第四区域和第五区域相邻的第六区域，以提供被配置为影响第二区域的第二反向击穿电压 第四区域和第五区域，其中第二反向击穿电压和第一反向击穿电压不同。

公开(公告)号：US20140001594A1

公开(公告)日：2014-01-02

申请号：US13537299

申请日：2012-06-29

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/66143

摘要： A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.

摘要翻译： 肖特基二极管包括具有中心部分和多个指状物的器件结构。 手指的远端覆盖泄漏电流控制（LCC）区域。 LCC区域相对较窄和深，终止于类似极性的掩埋层附近。 在反向偏压下，在位于掩埋层和LCC区域之间的有源区域中形成的耗尽区域占据有源区域的整个范围，从而提供载流子耗尽的壁。 类似的耗尽区发生在驻留在任何一对相邻手指之间的有源区域中。 如果手指包括纬向取向的指状物和纵向取向的指状物，则可能发生三个不同正交取向的耗尽区域封锁。 LCC区域的形成可以包括使用使用LCC植入物掩模的高剂量，低能量磷植入物，并且将隔离结构用作附加的硬掩模。

公开(公告)号：US20140061731A1

公开(公告)日：2014-03-06

申请号：US13605357

申请日：2012-09-06

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

摘要翻译： 一种器件包括半导体衬底，由半导体衬底支撑的第一和第二电极，彼此横向间隔开，并分别设置在半导体衬底的表面以形成欧姆接触和肖特基结。 该器件还包括半导体衬底中的导电通路区域，具有第一导电类型，并且沿第一和第二电极之间的导电路径设置，半导体衬底中的具有第二导电类型并设置在导电路径下方的掩埋区域 以及电耦合到所述掩埋区域的器件隔离区域，具有所述第二导电类型，并且限定所述器件的横向边界。 器件隔离区域电耦合到第二电极，使得在操作期间第二电极处的电压被施加到掩埋区域以耗尽导电路径区域。

公开(公告)号：US20140061715A1

公开(公告)日：2014-03-06

申请号：US13601831

申请日：2012-08-31

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/68 ,  H01L21/329

CPC分类号： H01L29/866 ,  H01L29/0692

摘要： A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

摘要翻译： 在一个实施例中，公开的齐纳二极管包括形成浅亚表面纬向齐纳结的阳极区域和阴极区域。 齐纳二极管还可以包括将阳极区域与位于远离齐纳结区域的触点和覆盖阳极区域的硅化物阻挡结构互连的阳极接触区域。 齐纳二极管还可以包括在阴极区域和相邻区域的侧边缘之间的接合处的一个或多个浅的子表面纵向p-n结。 相邻区域可以是诸如阳极接触区域的重掺杂区域。 在其他实施例中，齐纳二极管可以包括击穿电压升压区域，其包括位于阴极区域和阳极接触区域之间的较轻掺杂区域。

公开(公告)号：US09018673B2

公开(公告)日：2015-04-28

申请号：US13601831

申请日：2012-08-31

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC分类号： H01L29/866 ,  H01L29/0692

摘要： A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

摘要翻译： 在一个实施例中，公开的齐纳二极管包括形成浅亚表面纬向齐纳结的阳极区域和阴极区域。 齐纳二极管还可以包括将阳极区域与位于远离齐纳结区域的触点和覆盖阳极区域的硅化物阻挡结构互连的阳极接触区域。 齐纳二极管还可以包括在阴极区域和相邻区域的侧边缘之间的接合处的一个或多个浅的子表面纵向p-n结。 相邻区域可以是诸如阳极接触区域的重掺杂区域。 在其他实施例中，齐纳二极管可以包括击穿电压升压区域，其包括位于阴极区域和阳极接触区域之间的较轻掺杂区域。

公开(公告)号：US20140242762A1

公开(公告)日：2014-08-28

申请号：US14269825

申请日：2014-05-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L27/06

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

摘要翻译： 制造具有集成结型场效应晶体管（JFET）器件的肖特基二极管的方法包括沿着肖特基二极管的导通路径在半导体衬底中形成导电路径区域。 导电路径区域具有第一导电类型。 通过在具有第二导电类型的半导体衬底中形成器件隔离结构的阱来限定肖特基二极管的有源区的横向边界。 进行第二导电类型的掺杂剂的注入以在导电路径区域下的半导体衬底中形成掩埋JFET栅极区域。 植入物构造成进一步形成其中设置肖特基二极管的器件隔离结构。

公开(公告)号：US09741793B2

公开(公告)日：2017-08-22

申请号：US13448062

申请日：2012-04-16

申请人： Patrice M. Parris ,  Weize Chen

发明人： Patrice M. Parris ,  Weize Chen

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

摘要： An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.

公开(公告)号：US09537000B2

公开(公告)日：2017-01-03

申请号：US13792876

申请日：2013-03-11

申请人： Weize Chen ,  Patrice M. Parris

发明人： Weize Chen ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.

摘要翻译： 半导体器件包括具有表面的衬底，设置在衬底中的复合体区域，具有第一导电类型，并且包括在衬底的表面处的体接触区域和在操作期间形成沟道的阱， 源极区域，设置在与所述复合体区域相邻并具有第二导电类型的所述半导体衬底中;以及隔离区域，设置在所述本体接触区域和所述源极区域之间。 复合体区域还包括与源极区域相邻并且在源极区域附近的体导电路径区域，并且身体传导路径区域具有比阱更高的掺杂剂浓度水平。

公开(公告)号：US07740805B2

公开(公告)日：2010-06-22

申请号：US11095338

申请日：2005-03-31

申请人： Patrice M. Parris

发明人： Patrice M. Parris

IPC分类号： B01L3/00

CPC分类号： B01L3/502715 ,  B01L3/502707 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/023 ,  B01L2300/024 ,  B01L2300/0627 ,  B01L2300/0645 ,  B01L2400/0406 ,  B01L2400/0415 ,  G01N2035/00158

摘要： A device for analyzing a fluid sample is provided. The device includes a substrate, a trench formed in said substrate, and a processor. The trench includes a channel, a sample chamber, and a reagent chamber, each in fluid communication with each another. The sample chamber is configured to receive the fluid sample. The processor is integrally formed in the substrate and is in communication with the trench. The processor is configured to analyze the fluid sample. Methods for manufacturing the device are also provided.

摘要翻译： 提供了用于分析流体样品的装置。 该器件包括衬底，形成在所述衬底中的沟槽和处理器。 沟槽包括各自彼此流体连通的通道，样品室和试剂室。 样品室被配置为接收流体样品。 处理器一体地形成在基板中并且与沟槽连通。 处理器配置为分析流体样品。 还提供了用于制造该装置的方法。