公开(公告)号：US08406060B2

公开(公告)日：2013-03-26

申请号：US12949728

申请日：2010-11-18

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C16/04 ,  G11C16/06 ,  G06F13/00

Abstract: Subject matter disclosed herein relates to techniques to operate memory.

公开(公告)号：US08361833B2

公开(公告)日：2013-01-29

申请号：US12951304

申请日：2010-11-22

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L21/00

CPC classification number: H01L45/1286 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675

Abstract: A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

Abstract translation: 用于相变存储器的基本上平面的加热器可以向上延伸以逐渐接触硫族化物层。 结果，加热器和硫族化物之间的接触面积减小了。 在一些实施例中，这种减小的接触面积可以降低功耗。

公开(公告)号：US06815328B2

公开(公告)日：2004-11-09

申请号：US10001625

申请日：2001-10-24

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L214763

CPC classification number: H01L23/5226 ,  H01L21/768 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

公开(公告)号：US06677206B2

公开(公告)日：2004-01-13

申请号：US09740407

申请日：2000-12-19

Applicant: Matteo Patelmo ,  Federico Pio

Inventor： Matteo Patelmo ,  Federico Pio

IPC: H01L21336

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

Abstract translation: 一种包括多个存储单元的非易失性存储器件，每个存储单元形成为具有源区域的MOS晶体管，漏极区域和具有与其形成侧面的栅极; 以及设置在栅极侧面上的一个或多个电介质间隔物。 至少一个存储单元被定义为ON状态，并且至少一个存储单元被定义为OFF状态。 处于导通状态的存储单元包括漏极区域和轻扩散漏极（LDD）类型的源极区域，其特征在于，处于断开状态的存储器单元的至少一个漏极区域和至少一个源极区域由 一个或多个高掺杂剂区域。 处于OFF状态的存储单元由定义为源极区域，漏极区域和栅极的一个或多个有源区域的顶部上的硅化物层组成。

公开(公告)号：US06643184B2

公开(公告)日：2003-11-04

申请号：US10057767

申请日：2002-01-24

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C1604

CPC classification number: G11C16/16

Abstract: A method of erasing a flash memory integrated in a chip of semiconductor material and including at least one matrix of cells with a plurality of rows and a plurality of columns made in at least one insulated body, the cells of each row being connected to a corresponding word line; the method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.

公开(公告)号：US06445031B1

公开(公告)日：2002-09-03

申请号：US09322454

申请日：1999-05-28

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A byte-switch structure for electrically erasable and programmable non-volatile memories, includes a MOS transistor having a drain electrode coupled to a respective metal control gate line, a source electrode coupled to a respective polysilicon byte control line which is connected to control gate electrodes of all the memory cells of a same memory byte or word and is formed in an upper polysilicon layer, and a gate electrode coupled to a respective word line. The source and drain electrodes of the MOS transistor are respectively a first and a second doped regions of a first conductivity type formed in a semiconductor layer of a second conductivity type at opposite sides of the respective word line. The first and second doped regions are formed under the respective metal control gate line, and the polysilicon byte control gate line insulatively extends under the metal control gate line to overlap said first doped region, and contacts the first doped region through a respective contact opening in an underlying stack formed by an interpoly dielectric layer, a lower polysilicon layer and an oxide layer.

Abstract translation: 一种用于电可擦除和可编程非易失性存储器的字节开关结构，包括具有耦合到相应的金属控制栅极线的漏电极的MOS晶体管，耦合到相应多晶硅字节控制线的源电极，其连接到控制栅电极 相同存储器字节或字的所有存储器单元，并且形成在上多晶硅层中，以及耦合到相应字线的栅电极。 MOS晶体管的源电极和漏电极分别是在相应字线的相对侧形成在第二导电类型的半导体层中的第一导电类型的第一和第二掺杂区域。 第一和第二掺杂区域形成在相应的金属控制栅极线下方，并且多晶硅字节控制栅极线在金属控制栅极线下方绝缘地延伸以与所述第一掺杂区域重叠，并且通过相应的接触开口接触第一掺杂区域 由多层介电层，下多晶硅层和氧化物层形成的底层叠层。

公开(公告)号：US06437393B1

公开(公告)日：2002-08-20

申请号：US09636114

申请日：2000-08-10

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L2974

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

Abstract translation: 讨论了非易失性存储单元及其制造方法。 电池集成在半导体衬底中，并且包括具有在第一源区和漏区之间在衬底上突出的第一源极区，第一漏极区和栅极区的浮栅晶体管。 电池还包括具有第二源极区域，第二漏极区域和相应栅极区域的选择晶体管，在第二源极和漏极区域之间的衬底上突出。 第一和第二区域被轻掺杂，并且电池包括掩模元件。

公开(公告)号：US06309972B1

公开(公告)日：2001-10-30

申请号：US09451535

申请日：1999-12-01

Applicant: Federico Pio

Inventor： Federico Pio

IPC: C36C1600

CPC classification number: H01L21/31116 ,  H01L21/32136

Abstract: During critical plasma etching steps, the wafer's surface is illuminated with electromagnetic radiation in the visible and/or in the UV spectrum having an energy and power density sufficient to increase the reverse current through protective junctions on the wafer. These protective junctions provide electrical discharge paths for electrical charges picked up by exposed conductive parts of the wafer. The induced voltages are limited to values compatible with preserving the integrity of functional dielectric layers coupled to the exposed conductive parts and to the semiconductor substrate or to another conductive part.

Abstract translation: 在临界等离子体蚀刻步骤期间，晶片的表面被可见光和/或UV光谱中的电磁辐射照射，其能量和功率密度足以通过晶片上的保护结增加反向电流。 这些保护结提供了由晶片的暴露的导电部分拾取的电荷的放电路径。 感应电压被限制为与保持耦合到暴露的导电部件和半导体衬底或另一导电部件的功能电介质层的完整性兼容的值。

公开(公告)号：US06259132B1

公开(公告)日：2001-07-10

申请号：US09109487

申请日：1998-07-02

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/115 ,  H01L27/11524

Abstract: Array of electrically programmable non-volatile memory cells, each cell comprising a stacked-gate MOS transistor having a lower gate electrode, an upper gate electrode coupled to a row of the array, a first electrode associated with a column of the array and a second electrode separated from the first electrode by a channel region underlying said lower gate electrode, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell which identically to the electrically programmable non-volatile memory cells comprises a stacked-gate MOS transistor and is associated with a respective row and a respective column of the array, the ROM cell including means for allowing or not allowing the electrical separation between said respective column and the second electrode of the ROM cell, if the ROM cell must store a first logic state or, respectively, a second logic state.

Abstract translation: 阵列的电可编程非易失性存储单元，每个单元包括具有下栅电极的堆叠栅MOS晶体管，耦合到阵列行的上栅电极，与阵列的列相关联的第一电极和第二电极 电极通过所述下部栅极电极下方的沟道区域与第一电极分离，第一电极，第二电极和沟道区域形成为具有第一导电类型并具有第二导电类型的半导体材料层，至少包括 与电可编程非易失性存储单元相同的一个ROM存储器单元包括堆叠栅极MOS晶体管，并与阵列的相应行和相应的列相关联，ROM单元包括用于允许或不允许电分离的装置 在ROM单元的所述相应列和第二电极之间，如果ROM单元必须存储第一逻辑状态， 第二个逻辑状态。

公开(公告)号：US06180460B2

公开(公告)日：2001-01-30

申请号：US09337051

申请日：1999-06-21

Applicant: Carlo Cremonesi ,  Federico Pio ,  Nicola Zatelli

Inventor： Carlo Cremonesi ,  Federico Pio ,  Nicola Zatelli

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

Abstract translation: 用于制造具有以矩阵结构排列成行和列的存储单元的非易失性存储器的处理，其中源极线与所述行并联延伸并插入到所述行中，所述单元包括具有浮置栅极和控制栅极的MOS晶体管， 叠加第一和第二多晶硅层，该方法包括第一步骤，定义由氧化物薄膜覆盖并由场氧化物区域限定的有源区域的区域，第一多晶硅层沉积的第二步骤 通过第一掩模蚀刻第一多晶硅层以分离属于同一行矩阵的单元的浮动栅极的步骤，中间介电层和第二多晶硅层的沉积的第四步骤，第五步骤的定义 的行通过所述第二多晶硅层，中间介电层和第一多晶硅层的自对准选择性蚀刻，sel 在对应于在第三步骤期间去除了第一多晶硅层的区域的源极线挖掘中确定f-对准的选择性蚀刻以及在有源区域中的掺杂剂引入的第六步骤，用于形成源区域和 细胞排泄。 在第四步骤之前，对应于将形成挖掘的共同源极线的区域提供选择性引入掺杂剂，以形成比挖掘更深的掺杂区域。