公开(公告)号：US06551892B2

公开(公告)日：2003-04-22

申请号：US09891438

申请日：2001-06-25

申请人： Matteo Patelmo ,  Federico Pio

发明人： Matteo Patelmo ,  Federico Pio

IPC分类号： H01L2120

CPC分类号： H01L27/0255 ,  H01L27/0727 ,  Y10S438/983

摘要： A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

摘要翻译： 一种制造工艺，其形成在容纳第一N型导电区域且具有高于阱的掺杂水平的N型阱中形成的齐纳二极管，以及与第一导电区域邻接布置的第二P型导电区域。 第一导电区域通过具有与第一导电区域相同的掺杂水平的第三N型导电区域连接到覆盖待保护的栅极氧化物层的导电材料层。 第三导电区域，阱和衬底形成N + / N / P二极管，其在从形成MOS元件的栅极区域的多晶硅层的沉积期间保护集成器件制造期间的栅极氧化物层。

公开(公告)号：US06278159B1

公开(公告)日：2001-08-21

申请号：US09344426

申请日：1999-06-25

申请人： Matteo Patelmo ,  Federico Pio

发明人： Matteo Patelmo ,  Federico Pio

IPC分类号： H01L2362

CPC分类号： H01L27/0255 ,  H01L27/0727 ,  Y10S438/983

摘要： A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

公开(公告)号：US06677206B2

公开(公告)日：2004-01-13

申请号：US09740407

申请日：2000-12-19

申请人： Matteo Patelmo ,  Federico Pio

发明人： Matteo Patelmo ,  Federico Pio

IPC分类号： H01L21336

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

摘要翻译： 一种包括多个存储单元的非易失性存储器件，每个存储单元形成为具有源区域的MOS晶体管，漏极区域和具有与其形成侧面的栅极; 以及设置在栅极侧面上的一个或多个电介质间隔物。 至少一个存储单元被定义为ON状态，并且至少一个存储单元被定义为OFF状态。 处于导通状态的存储单元包括漏极区域和轻扩散漏极（LDD）类型的源极区域，其特征在于，处于断开状态的存储器单元的至少一个漏极区域和至少一个源极区域由 一个或多个高掺杂剂区域。 处于OFF状态的存储单元由定义为源极区域，漏极区域和栅极的一个或多个有源区域的顶部上的硅化物层组成。

公开(公告)号：US20140061575A1

公开(公告)日：2014-03-06

申请号：US13600777

申请日：2012-08-31

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L45/00 ,  G11C5/06 ,  H01L21/02

CPC分类号： H01L45/16 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/249 ,  H01L29/41758 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

摘要： Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

公开(公告)号：US07630263B2

公开(公告)日：2009-12-08

申请号：US11318053

申请日：2005-12-23

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： G11C7/02

CPC分类号： G11C29/026 ,  G11C7/14 ,  G11C16/04 ,  G11C16/28 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004

摘要： In a semiconductor memory device, a method for obtaining at least one reference cell adapted to be exploited as a generator of a reference signal, the reference signal depending on a value of an electrical characteristic of the at least one reference cell. The method includes providing a population of auxiliary cells, operating on said population of auxiliary cells for varying a value of the electrical characteristic thereof, in such a way that the varied values are statistically distributed in a range including a value of the electrical characteristic corresponding to the reference signal, and choosing the at least one reference cell, wherein choosing includes choosing at least one auxiliary cell in the population of auxiliary cells having the value of the electrical characteristic close to the value corresponding to the reference signal with a pre-defined tolerance.

摘要翻译： 在半导体存储器件中，一种用于获得至少一个参考单元的方法，所述至少一个参考单元适于被用作参考信号的发生器，所述参考信号取决于所述至少一个参考单元的电特性的值。 该方法包括提供一组辅助单元，其操作在所述辅助单元群上，用于改变其电特性的值，使得变化的值被统一分布在包括对应于 参考信号，以及选择至少一个参考小区，其中选择包括选择辅助小区群中的至少一个辅助小区，其具有接近与参考信号对应的值的电特性的值，具有预定公差 。

公开(公告)号：US07529136B2

公开(公告)日：2009-05-05

申请号：US11844480

申请日：2007-08-24

申请人： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

发明人： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

IPC分类号： G11C16/04

CPC分类号： G11C16/344

摘要： A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

摘要翻译： 一种用于操作闪存设备的方法。 存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。 该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元 目标值 将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元 细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

公开(公告)号：US06548355B2

公开(公告)日：2003-04-15

申请号：US09760069

申请日：2001-01-11

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

摘要： An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is isolated from the substrate by an oxide layer including a thinner tunnel portion and heavily doped regions formed under said tunnel portion and extending to beneath the drain region, and a selection transistor having a source region, a drain region and a gate region, wherein said source region is heavily doped and formed simultaneously with said heavily doped regions.

摘要翻译： 集成在半导体衬底中的EEPROM存储单元包括具有源极区域，漏极区域和从衬底突出的栅极区域的浮置栅极MOS晶体管，并且通过包括较薄隧道部分和重掺杂的氧化物层与衬底隔离 形成在所述隧道部分下方并延伸到漏极区域下方的区域，以及具有源极区域，漏极区域和栅极区域的选择晶体管，其中所述源极区域被重掺杂并与所述重掺杂区域同时形成。

公开(公告)号：US06307229B2

公开(公告)日：2001-10-23

申请号：US09081881

申请日：1998-05-19

申请人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

发明人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

摘要翻译： 一种具有半导体材料层中的存储单元矩阵的非易失性半导体存储器件结构。 存储单元位于矩阵的行和列的交点处。 每个存储单元包括连接到行中的一个的控制栅电极，连接到一列的第一电极和第二电极。 这些行包括在第一方向上彼此平行延伸的多晶硅条，并且所述列由在与第一方向正交的第二方向上彼此平行延伸的金属条形成。 短路金属带被耦合以使存储器单元的第二电极短路。 列和短路带分别形成在第一金属层和第二金属层之间，第二金属层与第二金属层叠在一起，并被电介质层电绝缘。

公开(公告)号：US6128219A

公开(公告)日：2000-10-03

申请号：US428683

申请日：1999-10-27

申请人： Federico Pio ,  Enrico Gomiero ,  Alberto Modelli ,  Paola Paruzzi

发明人： Federico Pio ,  Enrico Gomiero ,  Alberto Modelli ,  Paola Paruzzi

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/0433 ,  G11C16/34

摘要： A test structure is formed by an array of memory cells connected in parallel and including each a memory transistor and a select transistor connected in series. The gate terminals of the select transistors of all memory cells are biased to a value next to the threshold voltage of the select transistors. Therefore, in each memory cell, the drain current is limited by the memory transistor for control gate voltages below the threshold voltage of the memory transistor, and by the select transistor at higher voltages; for high control gate voltages, the drain current is clamped to a constant maximum value. Since the clamping effect of the select transistors acts on each memory cell, the total maximum current of the test structure may be held below a value causing a limitation in the current generated by the entire array because of the resistance in series to the output of the test structure. Thus also the right side of the threshold distribution may be evaluated and the presence of defective cells causing injection of electrons in the floating gate of the memory transistors may be detected.

摘要翻译： 测试结构由并行连接的存储单元的阵列形成，并且包括串联连接的存储晶体管和选择晶体管。 所有存储单元的选择晶体管的栅极端子被偏置成与选择晶体管的阈值电压相邻的值。 因此，在每个存储单元中，漏极电流被存储晶体管限制，用于控制栅极电压低于存储晶体管的阈值电压，并由选择晶体管处于较高电压; 对于高控制栅极电压，漏极电流被钳位到恒定的最大值。 由于选择晶体管的钳位效应作用于每个存储单元，所以测试结构的总最大电流可以被保持在导致由整个阵列产生的电流限制的值，因为与 测试结构。 因此，可以评估阈值分布的右侧，并且可以检测到在存储晶体管的浮动栅极中引起电子注入的缺陷单元的存在。

公开(公告)号：US6127224A

公开(公告)日：2000-10-03

申请号：US222024

申请日：1998-12-29

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

摘要翻译： 讨论了非易失性存储单元及其制造方法。 电池集成在半导体衬底中，并且包括具有在第一源区和漏区之间在衬底上突出的第一源极区，第一漏极区和栅极区的浮栅晶体管。 电池还包括具有第二源极区域，第二漏极区域和相应栅极区域的选择晶体管，在第二源极和漏极区域之间的衬底上突出。 第一和第二区域被轻掺杂，并且电池包括掩模元件。