公开(公告)号：US06841491B1

公开(公告)日：2005-01-11

申请号：US10039469

申请日：2001-11-08

Applicant: Sharmin Sadoughi ,  Krishnaswamy Ramkumar

Inventor： Sharmin Sadoughi ,  Krishnaswamy Ramkumar

IPC: H01L21/027 ,  H01L21/318 ,  H01L21/31

CPC classification number: H01L21/0276 ,  H01L21/3185

Abstract: A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.

Abstract translation: 一种用于制造半导体结构的工艺包括用第一工具在半导体衬底上沉积氮化物层，并在第一工具上在半导体衬底上沉积抗反射层。 氮化物层包括硅和氮。

公开(公告)号：US06838392B1

公开(公告)日：2005-01-04

申请号：US10119574

申请日：2002-04-09

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/02052 ,  H01L21/31111 ,  H01L21/76232

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

公开(公告)号：US06818558B1

公开(公告)日：2004-11-16

申请号：US10185470

申请日：2002-06-28

Applicant: Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

Inventor： Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

IPC: H01L21311

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/7882

Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

Abstract translation: 公开了形成电荷存储层的方法。 根据实施例，一种方法可以包括以第一气体流速比形成电荷存储层的第一部分（步骤102）的步骤，通过改变到第二气体形成电荷存储层的至少第二部分 流量比与第一气体流量比不同（步骤104），并且通过改变到与第二气体流量比不同的第三气体流量比形成至少第三部分的电荷存储层（ 步骤106）。

公开(公告)号：US06803321B1

公开(公告)日：2004-10-12

申请号：US10313049

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01I21302

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/3185

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract translation: 形成半导体结构的方法包括在叠层上形成氮化物层，并蚀刻氮化物层以形成与堆叠的侧面接触的间隔物。 叠层在半导体衬底上，堆叠包括（i）栅极层，包括硅，（ii）栅极层上的金属层，和（iii）金属层上的蚀刻停止层。 通过CVD形成气体，其中包含SixL2x的气体，L是氨基，X是1或2。

公开(公告)号：US06774452B1

公开(公告)日：2004-08-10

申请号：US10321965

申请日：2002-12-17

Applicant: Krishnaswamy Ramkumar ,  Sharmin Sadoughi

Inventor： Krishnaswamy Ramkumar ,  Sharmin Sadoughi

IPC: H01L2176

CPC classification number: H01L21/76229 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

Abstract translation: 公开了一种包括半导体衬底，半导体衬底中的隔离沟槽和半导体衬底中的对准沟槽的半导体结构。 该结构还包括电介质层和金属层。 介电层位于半导体衬底上并且在隔离沟槽和对准沟槽中。 电介质层填充隔离沟槽并且不填充对准沟槽。 金属层位于电介质层上。

公开(公告)号：US06773975B1

公开(公告)日：2004-08-10

申请号：US10326707

申请日：2002-12-20

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan ,  Shahin Sharifzadeh

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan ,  Shahin Sharifzadeh

IPC: H01L218238

CPC classification number: H01L21/823481 ,  H01L21/76229

Abstract: In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.

Abstract translation: 在一个实施例中，在形成浅沟槽隔离（STI）结构之前，通过形成栅极材料，例如栅极氧化物层和栅极多晶硅层来制造晶体管。 在此过程早期形成栅极材料可最大限度地减少STI结构暴露其角落的处理步骤。 此外，为了最小化掺杂剂的交叉扩散并有助于降低栅极电阻，可以使用包括阻挡层和金属层的金属堆叠作为栅极之间的导电线。 在一个实施例中，金属堆叠包括氮化钨的阻挡层和钨的金属层。

公开(公告)号：US06680516B1

公开(公告)日：2004-01-20

申请号：US10313267

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L2976

CPC classification number: H01L21/76897 ,  H01L29/42372

Abstract: A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Abstract translation: 半导体结构包括半导体衬底，半导体衬底上的栅极层，栅极层上的金属层以及金属层上的蚀刻停止层。 衬底与蚀刻停止层的顶部之间的距离是栅堆叠高度，栅叠层高度至多为2700埃。 此外，蚀刻停止层的厚度至少为800埃。

公开(公告)号：US08993453B1

公开(公告)日：2015-03-31

申请号：US13620071

申请日：2012-09-14

Applicant: Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.

Abstract translation: 描述了一种用于制造非易失性电荷陷阱存储器件及其装置的方法。 在一个实施例中，该方法包括在氧化室中提供衬底，其中衬底包括第一暴露的晶体面和第二暴露的晶面，并且其中第一暴露的晶面的晶体取向不同于 第二次暴露的晶面。 然后对基板进行自由基氧化处理，以在第一暴露的晶面上形成电介质层的第一部分，在第二暴露的晶面上形成电介质层的第二部分，其中电介质的第一部分的厚度 层大致等于电介质层的第二部分的厚度。

公开(公告)号：US08592891B1

公开(公告)日：2013-11-26

申请号：US13539463

申请日：2012-07-01

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

IPC: H01L29/76

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.

Abstract translation: 提供了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有设置在沟道区上方的氧化氮化物 - 氮化物 - 氧化物（ONNO）堆的存储晶体管。 ONNO堆叠包括设置在沟道区上方的隧道介电层，设置在隧道介电层上方的多层电荷捕获区，以及设置在多层电荷俘获区上方的阻挡介质层。 多层电荷捕获区域包括基本上无陷阱层，其包含富含氧的氮化物和设置在无阱层之上的陷阱致密层。 半导体器件还包括应变诱导结构，其包括设置在ONNO堆叠附近的应变诱导层，以增加多层电荷俘获区域的电荷保留。 还公开了其他实施例。

公开(公告)号：US20130210209A1

公开(公告)日：2013-08-15

申请号：US13428201

申请日：2012-03-23

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/792

Abstract: Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.

Abstract translation: 描述了将非易失性存储器件集成到MOS流中的方法的实施例。 通常，所述方法包括：在衬底的表面上形成电介质叠层，所述电介质堆叠包括覆盖所述衬底表面的隧道电介质和覆盖所述隧道电介质的电荷捕获层; 形成覆盖在所述电介质叠层上的盖层; 图案化所述盖层和所述电介质堆叠以在所述衬底的第一区域中形成存储器件的栅极叠层，并且从所述衬底的第二区域去除所述覆盖层和所述电荷俘获层; 以及进行氧化处理，以形成覆盖在第二区域中的衬底的表面上的MOS器件的栅极氧化物，同时对盖层进行氧化以形成覆盖电荷俘获层的阻挡氧化物。 还公开了其他实施例。