公开(公告)号：US10909443B2

公开(公告)日：2021-02-02

申请号：US16283887

申请日：2019-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Siva P. Adusumilli ,  Ruilong Xie ,  Julien Frougier

IPC: G06N3/04 ,  H01L27/24 ,  H01L45/00 ,  H01L29/872

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

公开(公告)号：US20200251498A1

公开(公告)日：2020-08-06

申请号：US16266307

申请日：2019-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edward J. Nowak

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: Structures for a memory cell and methods associated with forming and using such structures. The structure includes a silicon-on-insulator wafer including a device layer, a substrate, and a buried insulator layer between the device layer and the substrate. The structure further includes a field-effect transistor having first and second source/drain regions and a gate electrode that are over the buried insulator layer. A moat region is arranged in the substrate beneath the field-effect transistor, a well is arranged in the substrate beneath the moat region, and an isolation region extends through the device layer and the buried insulator layer into the substrate. The isolation region is arranged to surround a portion of the device layer defining an active region for the field-effect transistor and a portion of the moat region. A fence region, which extends between the well and the isolation region, surrounds the portion of the moat region.

公开(公告)号：US10658390B2

公开(公告)日：2020-05-19

申请号：US16031407

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Richard F. Taylor ,  Tamilmani Ethirajan

IPC: H01L27/12 ,  H01L29/10 ,  H03K17/687 ,  H01L21/762 ,  H03K17/693 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

公开(公告)号：US10381459B2

公开(公告)日：2019-08-13

申请号：US15865973

申请日：2018-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

IPC: H01L21/44 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/308 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

公开(公告)号：US10269707B2

公开(公告)日：2019-04-23

申请号：US15634135

申请日：2017-06-27

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L23/535 ,  H01L29/78 ,  H01L23/528

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US09929152B2

公开(公告)日：2018-03-27

申请号：US15198309

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823468 ,  H01L21/823487

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

公开(公告)号：US09847416B1

公开(公告)日：2017-12-19

申请号：US15351597

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Robert R. Robison ,  Brent A. Anderson

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7843 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

Abstract: Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.

公开(公告)号：US09786765B2

公开(公告)日：2017-10-10

申请号：US15044431

申请日：2016-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Andreas Scholze

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

公开(公告)号：US09659941B2

公开(公告)日：2017-05-23

申请号：US14754958

申请日：2015-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/11 ,  H01L21/28 ,  H01L29/417 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L27/1104 ,  H01L21/28008 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/45

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.

公开(公告)号：US09613861B2

公开(公告)日：2017-04-04

申请号：US14818419

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: Damascene wires with top via structures and methods of manufacture are provided. The semiconductor structure includes a damascene wiring structure with an integrally formed top via structure in self-alignment with the damascene wiring structure which is underneath the integrally formed top via structure.