公开(公告)号：US10819110B2

公开(公告)日：2020-10-27

申请号：US15906475

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Manjunatha G. Prabhu ,  Alain F. Loiseau ,  Mahbub Rashed ,  Sushama Davar

IPC: H02H9/04 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

公开(公告)号：US20180218981A1

公开(公告)日：2018-08-02

申请号：US15418001

申请日：2017-01-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Irene Y. L. Lin ,  Lei Yuan ,  Mahbub Rashed

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  G06F17/50

CPC classification number: H01L23/5286 ,  G06F17/5077 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11887

Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.

公开(公告)号：US20180040631A1

公开(公告)日：2018-02-08

申请号：US15226867

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L27/118 ,  H01L29/78

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/785 ,  H01L2027/11838 ,  H01L2027/11875 ,  H01L2027/11885

Abstract: At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are formed in a vertical configuration in a first metal layer of a memory cell. A second set of metal features are formed in a unidirectional horizontal configuration in a second metal layer of the memory cell. A third set of metal features are formed in the unidirectional horizontal configuration in a second metal layer of a functional cell for providing routing compatibility between the memory cell and the functional cell. The memory cell is placed adjacent to the functional cell for forming an integrated circuit device.

公开(公告)号：US09634003B2

公开(公告)日：2017-04-25

申请号：US15063563

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US09530780B2

公开(公告)日：2016-12-27

申请号：US15140548

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

Abstract translation: 公开了一种用于提供具有小型化位单元的SRAM位单元的方法，没有本地互连层，具有改进的平版印刷可印刷性和使能方法。 实施例包括在M1层中提供包括第一字线，第一位线，第二位线，第一接地线，第二接地线，第二锁存线或其组合的第一颜色结构，其中第一 颜色结构包括比边缘长的侧边缘; 在M1层中提供第二颜色结构，包括第二字线，第一电源线，第二电源线，第一锁存线或其组合，其中第二颜色结构包括比尖端边缘长的侧边缘; 以及形成包括所述第一颜色结构和所述第二颜色结构的位单元，其中相邻的尖端边缘包括第一颜色结构的尖端边缘和第二颜色结构的尖端边缘。

公开(公告)号：US20160336183A1

公开(公告)日：2016-11-17

申请号：US14712767

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L21/285 ,  H01L29/78 ,  H01L21/67 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/401 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein for processing a semiconductor wafer using a continuous active area design for manufacturing a finFET device. A first gate structure of a continuous active area design is formed in a first layer of the wafer. A first hard mask layer is deposited. A portion of the first hard mask layer is removed based upon a first trench silicide (TS) pattern and a second TS pattern. A full stripe first trench silicide (TS) structure and a second TS structure are formed. A first TS capping layer is deposited above the first TS structure and a second TS capping. The first TS capping layer is removed and a source/drain contact structure (CA) is formed above the first TS structure in a second layer of the semiconductor wafer. A gate contact structure (CB) is formed above the gate structure in the second layer.

Abstract translation: 本文公开的至少一种方法，装置和系统，用于使用用于制造finFET器件的连续有源区域设计来处理半导体晶片。 连续有源区域设计的第一栅极结构形成在晶片的第一层中。 沉积第一个硬掩模层。 基于第一沟槽硅化物（TS）图案和第二TS图案去除第一硬掩模层的一部分。 形成全条纹第一沟槽硅化物（TS）结构和第二TS结构。 第一TS封装层沉积在第一TS结构上方，并且第二TS覆盖层。 去除第一TS封盖层，并且在半导体晶片的第二层中的第一TS结构之上形成源极/漏极接触结构（CA）。 栅极接触结构（CB）形成在第二层中的栅极结构的上方。

公开(公告)号：US09391080B1

公开(公告)日：2016-07-12

申请号：US14698066

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

公开(公告)号：US09337099B1

公开(公告)日：2016-05-10

申请号：US14610260

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L21/44 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract translation: 提供了用于使具有不同大小的扩散区域的两个电池邻接的方法以及所得到的装置。 实施例包括：通过在两个单元之间的边界处形成虚拟栅极来邻接具有第一漏极和源极扩散区域的第一单元和具有大于第一扩散区域的第二漏极和源极扩散区域的第二单元; 形成连续的漏极扩散区域，其具有与伪栅极交叉的上部，并且包围整个第一漏极扩散区域和第二漏极扩散区域的一部分，并且具有从伪栅极开始的下部，并且包围第二漏极扩散区域的剩余部分 ; 形成作为连续漏极扩散区域的镜像的连续源极扩散区域; 以及在连续的漏极和源极扩散区之间在虚拟栅极之间形成多边形掩模，但是与连续的漏极和源极扩散区分离。

公开(公告)号：US20150331988A1

公开(公告)日：2015-11-19

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US09159724B2

公开(公告)日：2015-10-13

申请号：US14161063

申请日：2014-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Wang ,  Yuansheng Ma ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region.

Abstract translation: 公开了一种使用扩散接触结构提供基于交叉耦合的设计的方法。 实施例包括在衬底上提供第一和第二栅极结构; 提供横跨所述第一栅极结构，所述第二栅极结构或其组合的栅极截止区域; 在第一栅极结构上提供第一栅极接触; 在所述第二栅极结构上提供第二栅极接触; 以及提供将所述第一栅极接触耦合到所述第二栅极接触的扩散接触结构，所述扩散接触结构在所述栅极切割区域内具有顶点。