公开(公告)号：US20120079458A1

公开(公告)日：2012-03-29

申请号：US13137208

申请日：2011-07-28

申请人： Michael John Williams ,  Richard Roy Grisenthwaite

发明人： Michael John Williams ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/44

CPC分类号： G06F11/3648 ,  G06F9/30189

摘要： A data processing apparatus is provided comprising processing circuitry and instruction decoding circuitry. The data processing apparatus is capable of operating at a plurality of different privilege. Processing circuitry of the data processing apparatus imposes on program instructions different access permissions to at least one of a memory and a set of registers at different ones of the different privilege levels. A debug privilege-level switching instruction is provided and decoding circuitry is responsive to this instruction to switch the processing circuitry from a current privilege level to a target privilege level if the processing circuitry is in a debug mode. However, if the processing circuitry is in a non-debug mode the instruction decoding circuitry prevents execution of the privilege-level switching instruction regardless of the current privilege level.

摘要翻译： 提供了包括处理电路和指令解码电路的数据处理装置。 数据处理装置能够以多个不同的特权进行操作。 数据处理装置的处理电路对不同特权级别的存储器和一组寄存器中的至少一个对程序指令施加不同的访问权限。 提供调试权限级别切换指令，并且如果处理电路处于调试模式，则解码电路响应于该指令将处理电路从当前特权级别切换到目标特权级别。 然而，如果处理电路处于非调试模式，则指令解码电路防止执行特权级切换指令，而不管当前特权级别如何。

公开(公告)号：US08041897B2

公开(公告)日：2011-10-18

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓存，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被布置以实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该缓存中选择一个或多个用于逐出的数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US08010772B2

公开(公告)日：2011-08-30

申请号：US12068448

申请日：2008-02-06

申请人： Daniel Kershaw ,  Lee Douglas Smith ,  David James Seal ,  Richard Roy Grisenthwaite

发明人： Daniel Kershaw ,  Lee Douglas Smith ,  David James Seal ,  Richard Roy Grisenthwaite

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/322 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30101 ,  G06F12/145 ,  G06F2212/1004

摘要： Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.

摘要翻译： 存储器地址空间被划分为域，并且指令访问控制电路用于检测何时提取要执行的指令的存储器地址已经越过域边界并被改变，并且在这种情况下进行检查以确保在 新域名是允许的表单的允许指令。 允许的指令可以被布置为除指令访问控制电路之外的不操作指令，以便有助于向后兼容性。

公开(公告)号：US20110202740A1

公开(公告)日：2011-08-18

申请号：US12656849

申请日：2010-02-17

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F12/14

CPC分类号： G06F12/145 ,  G06F12/1009

摘要： Apparatus for data processing 2 is provided with processing circuitry 8 which operates in one or more secure modes 40 and one or more non-secure modes 42. When operating in a non-secure mode, one or more regions of the memory are inaccessible. A memory management unit 24 is responsive to page table data to manage accesses to the memory which includes a secure memory 22 and a non-secure memory 6. Secure page table data 36, 38 is used when operating in one of the secure modes. A page table entry within the hierarchy of page tables of the secure page table data includes a table security field 68, 72 indicating whether or not a further page table pointed to by that page table entry is stored within the secure memory 22 or the non-secure memory 6. If any of the page tables associated with a memory access are stored within the non-secure memory 6, then the memory access is marked with a table attribute bit NST indicating that the memory access should be treated as non-secure.

摘要翻译： 用于数据处理2的装置设置有处理电路8，其在一个或多个安全模式40和一个或多个非安全模式42中操作。当以非安全模式操作时，存储器的一个或多个区域是不可访问的。 存储器管理单元24响应于页表数据来管理对包括安全存储器22和非安全存储器6的存储器的访问。当以安全模式之一操作时，使用安全页表数据36,38。 在安全页表数据的页表的层次结构中的页表条目包括表安全字段68,72，指示该页表项所指向的另一页表是否存储在安全存储器22内， 如果与存储器访问相关联的任何页表存储在非安全存储器6内，则存储器访问用表属性位NST标记，指示存储器访问应被视为非安全的。

公开(公告)号：US20110125944A1

公开(公告)日：2011-05-26

申请号：US12923906

申请日：2010-10-13

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request.

摘要翻译： 公开了一种用于经由互连向接收方设备发出交易请求的发起者设备。 所述发起者设备包括：用于从所述互连接收请求并向所述互连发出请求的至少一个端口; 用于产生屏障事务请求的屏障发生器，所述屏障事务请求向所述互连指示通过所述互连的事务请求流内的至少一些事务请求的排序应该通过不允许重新排序所述事务中的至少一些来维持 关于屏障交易请求的交易请求流中的屏障事务请求之前发生的请求; 其中响应于接收到查询至少一个事务请求的子集的进程的同步请求，所述发起者设备响应于所述事务请求的所述至少一个子集内的任何待处理的事务请求的动作，并在所述屏障上生成屏障事务请求 并且经由至少一个端口向互连发出屏障事务请求，并且响应于接收到对屏障事务请求的响应来发出确认信号作为对同步请求的响应。

公开(公告)号：US20110119448A1

公开(公告)日：2011-05-19

申请号：US12923725

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request.

摘要翻译： 公开了一种用于数据处理装置的互连电路。 互连电路被配置为提供数据路由，至少一个启动器设备可经由该路径访问至少一个接收设备。 所述互连电路包括：用于接收来自所述发起者设备的交易请求的至少一个输入; 至少一个用于向所述接收方设备输出交易请求的输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的多条路径; 其中所述交易请求中的至少一个包括数据存储维护请求，请求在所述数据处理设备内的数据存储器上执行数据存储维护操作; 以及用于将所接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为通过沿着所述多个路径中的至少一个路径发送所述数据存储维护操作来响应于所述数据存储维护操作的接收，所述控制电路被配置为维持在 在沿所述多个路径中的至少一个路径传递的事务请求流内的至少一些关于屏障事务请求的事务请求，使得在事务请求流中的数据存储维护请求之后的至少一些事务请求是 通过屏障事务请求在数据存储维护请求之后。

公开(公告)号：US07707394B2

公开(公告)日：2010-04-27

申请号：US11442593

申请日：2006-05-30

申请人： Edmond John Simon Ashfield ,  Michael John Williams ,  John Michael Horley ,  Richard Roy Grisenthwaite

发明人： Edmond John Simon Ashfield ,  Michael John Williams ,  John Michael Horley ,  Richard Roy Grisenthwaite

IPC分类号： G06F11/36

CPC分类号： G06F9/3804 ,  G06F9/3844 ,  G06F11/3447 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/88 ,  Y02D10/34

摘要： Tracing logic for monitoring a stream of processing instructions from a program being processed by a data processor is disclosed, said tracing logic comprising monitoring logic operable to detect processing of said instructions in said instruction stream; detect which of said instructions in said instruction stream are conditional direct branch instructions, which of said instructions in said instruction stream are conditional indirect branch instructions and which of said instructions in said instruction stream are unconditional indirect branch instructions; said tracing logic further comprising compression logic operable to: designate said conditional direct branch instructions, said conditional indirect branch instructions and said indirect branch instructions as marker instructions; for each marker instruction, output an execution indicator indicating if said marker instruction has executed or a non-execution indicator indicating if said marker instruction has not executed and not output data relating to previously processed instructions that are not marker instructions.

摘要翻译： 公开了一种用于从由数据处理器处理的程序监视处理指令流的跟踪逻辑，所述跟踪逻辑包括可操作以检测所述指令流中的所述指令的处理的监视逻辑; 检测所述指令流中的哪个指令是条件直接分支指令，所述指令流中的哪个指令是条件间接分支指令，以及所述指令流中的所述指令中的哪一个是无条件间接分支指令; 所述跟踪逻辑还包括压缩逻辑，可操作用于：将所述条件直接分支指令，所述条件间接分支指令和所述间接分支指令指定为标记指令; 对于每个标记指令，输出指示所述标记指令是否已经执行的执行指示符或者指示是否所述标记指令未被执行的非执行指示符，而不输出与先前处理过的指令不是标记指令有关的数据。

公开(公告)号：US20100094613A1

公开(公告)日：2010-04-15

申请号：US12453806

申请日：2009-05-22

申请人： Stewart David Biles ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Stewart David Biles ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/455 ,  G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/45583

摘要： A data processing apparatus 12 is provided with a memory management unit 24 which triggers memory aborts. When a memory abort occurs, data characterising the memory abort is written to a fault status register 28 (memory-abort register). The data characterising the memory abort includes data identifying a register number associated with the memory access which gave rise to the memory abort. This register identifying data is used to emulate the action of the memory access instruction without having to read the program instruction lead to the memory abort. This is useful in providing virtualisation support for a virtual data processing apparatus 2.

摘要翻译： 数据处理装置12设置有触发存储器中止的存储器管理单元24。 当发生存储器中止时，表征存储器中止的数据被写入故障状态寄存器28（存储器中止寄存器）。 表征存储器中止的数据包括识别与存储器访问相关联的寄存器号的数据，这导致存储器中止。 该寄存器识别数据用于模拟存储器访问指令的动作，而不必读取导致存储器中止的程序指令。 这在为虚拟数据处理设备2提供虚拟化支持方面是有用的。

公开(公告)号：US20100005269A1

公开(公告)日：2010-01-07

申请号：US12216253

申请日：2008-07-01

申请人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/1036

摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.

摘要翻译： 公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。 地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目 存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

公开(公告)号：US20090193297A1

公开(公告)日：2009-07-30

申请号：US12318442

申请日：2008-12-30

申请人： Michael John Williams ,  Richard Roy Grisenthwaite ,  Andrew Brookfield Swaine ,  John Michael Horley

发明人： Michael John Williams ,  Richard Roy Grisenthwaite ,  Andrew Brookfield Swaine ,  John Michael Horley

IPC分类号： G06F11/28

CPC分类号： G06F11/3636

摘要： A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing a sequence of program instructions, each program instruction having one or more associated memory addresses. The data processing system has diagnostic circuitry 10 for performing diagnostic operations on the processor core. Diagnostic control circuitry 12 is provided which is responsive to current values of the virtual machine identifier, the context identifier and at least one of the one or more associated memory addresses to trigger the diagnostic circuitry 10 to perform diagnostic operations.

摘要翻译： 数据处理系统1具有处理器核心2，其可编程以充当多个虚拟机中的一个，每个虚拟机由虚拟机标识符标识，每个虚拟机以每个由上下文标识符标识的多个上下文之一起作用， 上下文执行程序指令序列，每个程序指令具有一个或多个关联的存储器地址。 数据处理系统具有用于在处理器核上进行诊断操作的诊断电路10。 提供了诊断控制电路12，其响应虚拟机标识符，上下文标识符的当前值和一个或多个相关联的存储器地址中的至少一个来触发诊断电路10执行诊断操作。