公开(公告)号：US07434152B2

公开(公告)日：2008-10-07

申请号：US11127810

申请日：2005-05-12

申请人： Giovanni Naso

发明人： Giovanni Naso

IPC分类号： G06F7/02 ,  H03M13/00

CPC分类号： G11C29/40

摘要： Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.

摘要翻译： 具有正常操作模式和测试操作模式的存储器件在质量程序中是有用的。 测试操作模式包括具有多于一个压缩级别的数据压缩测试模式。 读取和验证重复测试模式所需的时间可以减少，因为仅需要读取存储器件的单词的一小部分以确定存储器件准确地写入和存储数据值的能力。 选择性地禁用输出，如果一组单词的一个单词的位位置具有与多个单词组的单词的任何剩余单词不同的数据值。

公开(公告)号：US07164607B2

公开(公告)日：2007-01-16

申请号：US11142114

申请日：2005-06-01

申请人： Girolamo Gallo ,  Giuliano Gennaro Imondi ,  Giovanni Naso ,  Tommaso Vali

发明人： Girolamo Gallo ,  Giuliano Gennaro Imondi ,  Giovanni Naso ,  Tommaso Vali

IPC分类号： G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1021 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1066

摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.

摘要翻译： 包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

公开(公告)号：US07145799B2

公开(公告)日：2006-12-05

申请号：US11170880

申请日：2005-06-30

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C16/22

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。

公开(公告)号：US20060083061A1

公开(公告)日：2006-04-20

申请号：US11293760

申请日：2005-12-02

申请人： Goiovanni Santin ,  Giovanni Naso

发明人： Goiovanni Santin ,  Giovanni Naso

IPC分类号： G11C14/00

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/20 ,  G11C16/26 ,  G11C17/18

摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

公开(公告)号：US20050207233A1

公开(公告)日：2005-09-22

申请号：US11142114

申请日：2005-06-01

申请人： Girolamo Gallo ,  Giuliano Imondi ,  Giovanni Naso ,  Tommaso Vali

发明人： Girolamo Gallo ,  Giuliano Imondi ,  Giovanni Naso ,  Tommaso Vali

IPC分类号： G11C7/10 ,  G11C5/00

CPC分类号： G11C7/106 ,  G11C7/1021 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1066

摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.

摘要翻译： 包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

公开(公告)号：US06947323B2

公开(公告)日：2005-09-20

申请号：US10698752

申请日：2003-10-31

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C7/24 ,  G11C16/00 ,  G11C16/04 ,  G11C16/22 ,  G11C17/00

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。