公开(公告)号：US20130064855A1

公开(公告)日：2013-03-14

申请号：US13611976

申请日：2012-09-12

申请人： Anna Karolina Palucka ,  Jacques F. Banchereau ,  Florentina Marches ,  Chun Yu ,  SangKon Oh ,  Te-Chia Wu

发明人： Anna Karolina Palucka ,  Jacques F. Banchereau ,  Florentina Marches ,  Chun Yu ,  SangKon Oh ,  Te-Chia Wu

IPC分类号： A61K31/716 ,  A61K39/00 ,  A61P35/00

CPC分类号： A61K39/0011 ,  A61K31/716 ,  A61K35/15 ,  A61K2039/5154

摘要： Compositions and methods for the treatment of cancer disclosed herein. The method of the present invention comprises administration of compositions comprising β-glucan, a natural ligand for dectin-1, to block OX40L expression on tumor associated mDCs by blocking STAT6 phosphorylation. The β-glucan-treated mDCs secrete higher levels of IL-12p70 and do not expand TNFα and IL-13-producing CD4+ T cells, further resulting in inhibition of Th2 responses. Thus, compositions disclosed herein reprogram the function of mDCs in breast tumor microenvironment and turn tumor promoting Th2-type chronic inflammation into Th1-type acute inflammation that are able to reject tumors. The present invention finds particular uses for the intratumoral administration of the composition thereby directly binding to and directing a Th1-type acute inflammation.

摘要翻译： 本文公开的用于治疗癌症的组合物和方法。 本发明的方法包括施用包含葡聚糖的组合物，其是dectin-1的天然配体，通过阻断STAT6磷酸化阻断肿瘤相关mDC上的OX40L表达。 葡聚糖处理的mDC分泌更高水平的IL-12p70，不扩大TNFα和IL-13产生的CD4 + T细胞，进一步导致Th2应答的抑制。 因此，本文公开的组合物重新编码mDC在乳腺肿瘤微环境中的功能，并将肿瘤促进Th2型慢性炎症转化为能够排斥肿瘤的Th1型急性炎症。 本发明特别用于肿瘤内施用组合物，从而直接结合并导向Th1型急性炎症。

公开(公告)号：US08355028B2

公开(公告)日：2013-01-15

申请号：US11830667

申请日：2007-07-30

申请人： Guofang Jiao ,  Alexei V. Bourd ,  Chun Yu ,  Lingjun Chen ,  Yun Du

发明人： Guofang Jiao ,  Alexei V. Bourd ,  Chun Yu ,  Lingjun Chen ,  Yun Du

IPC分类号： G06T1/00

CPC分类号： G06T1/60 ,  G06T15/005

摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.

摘要翻译： 执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。 编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。 硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

公开(公告)号：US20120185671A1

公开(公告)日：2012-07-19

申请号：US13007333

申请日：2011-01-14

申请人： Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

发明人： Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

IPC分类号： G06F9/38

CPC分类号： G06F15/17325

摘要： This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

摘要翻译： 本公开描述了用于利用并行处理单元来扩展通用图形处理单元（GPGPU）的架构以允许基于流水线的应用的有效处理的技术。 这些技术包括配置连接到作为处理流水线的阶段的并行处理单元的本地存储器缓冲器，以保持用于在并行处理单元之间传送的数据。 本地存储缓冲器允许并行处理单元之间的片上，低功耗，直接数据传输。 本地存储器缓冲器可以包括基于硬件的数据流控制机制，以使得能够在并行处理单元之间传送数据。 以这种方式，数据可以经由本地存储器缓冲器直接从一个并行处理单元传递到处理流水线中的下一个并行处理单元，实际上将并行处理单元转换成一系列流水线级。

公开(公告)号：US08022960B2

公开(公告)日：2011-09-20

申请号：US11677986

申请日：2007-02-22

申请人： Chun Yu

发明人： Chun Yu

IPC分类号： G06T11/40 ,  G09G5/36

CPC分类号： G06F12/0846 ,  G06F12/0864 ,  G06F12/0875 ,  G06F2212/601

摘要： Techniques for dynamically configuring a texture cache are disclosed. During a texture mapping process of a three-dimensional (3D) graphics pipeline, if the batch is for single texture mapping, the texture cache is configured as a n-way set-associative texture cache. However, if the batch is for multi-texture mapping the n-way set-associated texture cache is divided into at n/M-way set-associative sub-caches where n and M are integers greater than 1 and n is divisible by M.

摘要翻译： 公开了用于动态配置纹理缓存的技术。 在三维（3D）图形流水线的纹理映射处理期间，如果批次用于单个纹理映射，则纹理高速缓存被配置为n路设置关联纹理高速缓存。 然而，如果批次用于多纹理映射，则n路集合关联纹理高速缓存分为n / M路集合关联子缓存，其中n和M是大于1的整数，n可以被M整除 。

公开(公告)号：US07944442B2

公开(公告)日：2011-05-17

申请号：US11609762

申请日：2006-12-12

申请人： Angus M. Dorbie ,  Alexei V. Bourd ,  Chun Yu

发明人： Angus M. Dorbie ,  Alexei V. Bourd ,  Chun Yu

IPC分类号： G06T15/40

CPC分类号： G06T11/40 ,  G06T2210/12

摘要： The system includes a shape buffer manager configured to store coverage data in the shape buffer. The coverage data indicates whether each mask pixel is a covered pixel or an uncovered pixel. A mask pixel is a covered pixel when a shape to be rendered on a screen covers the mask pixel such that one or more coverage criteria is satisfied and is an uncovered pixel when the shape does not cover the mask pixel such that the one or more coverage criteria are satisfied. A bounds primitive rasterizer is configured to rasterize a bounds primitive that bounds the shape. The bounds primitive is rasterized into primitive pixels that each corresponds to one of the mask pixels. A pixel screener is configured to employ the coverage data from the shape buffer to screen the primitive pixels into retained pixels and discarded pixels. The retained pixels each corresponds to a mask pixel that the coverage data indicates is a covered pixel and the discarded pixels each correspond to a mask pixels that the coverage data indicates is an uncovered pixel. The system also includes an attribute generator configured to generate pixel attributes for the retained primitive pixels and also configured not to generate pixel attributes for the discarded primitive pixels.

摘要翻译： 该系统包括形状缓冲器管理器，其被配置为将覆盖数据存储在形状缓冲器中。 覆盖数据指示每个掩模像素是被覆盖像素还是未覆盖像素。 当要在屏幕上呈现的形状覆盖掩模像素使得满足一个或多个覆盖准则并且当形状不覆盖掩模像素时是未被覆盖的像素，使得一个或多个覆盖 标准满足。 边界原始光栅化器被配置为光栅化限制形状的边界原语。 边界原语被光栅化为原始像素，每个像素对应于一个掩码像素。 像素筛选器被配置为使用来自形状缓冲器的覆盖数据来将原始像素屏蔽到保留的像素和丢弃的像素中。 保留像素分别对应于覆盖数据指示为被覆盖像素的掩码像素，并且丢弃的像素各自对应于覆盖数据指示的掩模像素是未覆盖的像素。 该系统还包括属性生成器，其被配置为生成被保留的原始像素的像素属性，并且还被配置为不为所丢弃的原始像素生成像素属性。

公开(公告)号：US20090265528A1

公开(公告)日：2009-10-22

申请号：US12106654

申请日：2008-04-21

申请人： Yun Du ,  Chun Yu ,  Guofang Jiao ,  Stephen Molloy

发明人： Yun Du ,  Chun Yu ,  Guofang Jiao ,  Stephen Molloy

IPC分类号： G06F9/30

CPC分类号： G06T15/005 ,  G06F8/47

摘要： The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision. The controller then causes the selected execution unit to execute the instruction with the indicated data precision using the graphics data associated with the instruction.

摘要翻译： 本公开涉及一种能够使用不同执行单元执行混合精度（例如，全精度，半精度）指令的可编程流式处理器。 各种执行单元都能够使用图形数据来执行特定精度级别的指令。 示例性可编程着色器处理器包括控制器和多个执行单元。 控制器被配置为接收用于执行的指令并且接收用于执行指令的数据精度的指示。 控制器还被配置为接收单独的转换指令，该指令在执行时将与指令相关联的图形数据转换为所指示的数据精度。 当可操作时，控制器基于指示的数据精度选择一个执行单元。 然后，控制器使所选择的执行单元使用与指令相关联的图形数据，以指示的数据精度执行指令。

公开(公告)号：US20090113402A1

公开(公告)日：2009-04-30

申请号：US11925476

申请日：2007-10-26

申请人： Lingjun Chen ,  Guofang Jiao ,  Yun Du ,  Chun Yu

发明人： Lingjun Chen ,  Guofang Jiao ,  Yun Du ,  Chun Yu

IPC分类号： G06F9/45

CPC分类号： G06F8/41

摘要： A server is disclosed that includes an interface to a data communication network, a compiler library that stores a plurality of different compilers, and compiler selection logic responsive to data received at the interface and including logic. The compiler selection logic is configured to select one of the plurality of different compilers based on an evaluation of the received data. The selected compiler generates compiled output data and the compiled output data is communicated over the data communication network to a client.

摘要翻译： 公开了一种服务器，其包括对数据通信网络的接口，存储多个不同编译器的编译器库，以及响应于在接口处接收的数据并包括逻辑的编译器选择逻辑。 编译器选择逻辑被配置为基于对接收到的数据的评估来选择多个不同编译器之一。 所选择的编译器生成编译的输出数据，并且编译的输出数据通过数据通信网络传送到客户机。

公开(公告)号：US20090096797A1

公开(公告)日：2009-04-16

申请号：US11870597

申请日：2007-10-11

申请人： Yun Du ,  Chun Yu ,  Guofang Jiao ,  Stephen Molloy

发明人： Yun Du ,  Chun Yu ,  Guofang Jiao ,  Stephen Molloy

IPC分类号： G06F15/80

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06T1/20 ,  Y02D10/171 ,  Y02D50/20

摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.

摘要翻译： 这里公开了与图形处理单元一起使用的功率控制器。 功率控制器监视，管理和控制提供给图形处理单元的管线的组件的电力。 功率控制器基于由电力控制器与流水线部件相关联的状态信息来确定是否以及在何种程度上向管道部件提供功率。 功率控制器能够使用接收到的状态信息来识别趋势，并且基于所识别的趋势来确定是否以及在何种程度上向管道部件供电。

公开(公告)号：US20090033672A1

公开(公告)日：2009-02-05

申请号：US11830667

申请日：2007-07-30

申请人： Guofang Jiao ,  Alexei V. Bourd ,  Chun Yu ,  Lingjun Chen ,  Yun Du

发明人： Guofang Jiao ,  Alexei V. Bourd ,  Chun Yu ,  Lingjun Chen ,  Yun Du

IPC分类号： G09G5/36

CPC分类号： G06T1/60 ,  G06T15/005

摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.

摘要翻译： 执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。 编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。 硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

公开(公告)号：US20080201716A1

公开(公告)日：2008-08-21

申请号：US11677362

申请日：2007-02-21

申请人： Yun Du ,  Guofang Jiao ,  Chun Yu

发明人： Yun Du ,  Guofang Jiao ,  Chun Yu

IPC分类号： G06F9/46

CPC分类号： G06F12/0842 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/45558 ,  G06F9/5016 ,  G06F12/10 ,  G06F2009/45579 ,  G06F2009/45583 ,  Y02D10/13 ,  Y02D10/22

摘要： A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, data, and state information for the applications and assignable processing units to perform various types of processing for the applications. The configurable storage resources may include an instruction cache to store instructions for the applications, register banks to store data for the applications, context registers to store state information for threads of the applications, etc. The processing units may include an arithmetic logic unit (ALU) core, an elementary function core, a logic core, a texture sampler, a load control unit, a flow controller, etc. The multimedia processor allocates a configurable portion of the storage resources to each application and dynamically assigns the processing units to the applications as requested by these applications.

摘要翻译： 一种设备包括多媒体处理器，其可以同时支持用于各种类型的多媒体（例如图形，音频，视频，照相机，游戏等）的多个应用。多媒体处理器包括可配置的存储资源以存储用于应用的指令，数据和状态信息 以及可分配处理单元来执行用于应用的各种类型的处理。 可配置的存储资源可以包括用于存储用于应用的指令的指令高速缓存，寄存器组存储用于应用的数据，上下文寄存器以存储用于应用的线程的状态信息等。处理单元可以包括算术逻辑单元（ALU ）核心，基本功能核心，逻辑核心，纹理采样器，负载控制单元，流量控制器等。多媒体处理器将存储资源的可配置部分分配给每个应用，并且将处理单元动态地分配给应用 按照这些应用的要求。