公开(公告)号：US5887024A

公开(公告)日：1999-03-23

申请号：US780145

申请日：1996-12-26

申请人： Xiaoling Qin ,  Kunihiko Suzuki ,  Guoliang Shou ,  Changming Zhou ,  Jie Chen

发明人： Xiaoling Qin ,  Kunihiko Suzuki ,  Guoliang Shou ,  Changming Zhou ,  Jie Chen

IPC分类号： H03H11/04 ,  H03H17/02 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC分类号： H03H11/04 ,  H03H17/02

摘要： The present invention provides a matched filter which can refresh an entire while keeping the speed of a calculation comparable to a small sized circuit. The first and second addition circuits of a matched filter of the present invention are classified into a plurality of groups, the first and second auxiliary adders replace functions for the groups of the first and second adders respectively. The outputs of the first and second adders are then inputted to the first and second subtractors, respectively, and the refreshing means appropriately refreshes the groups replaced by the first and second auxiliary adders. Further, the present invention decreases the number of auxiliary sapling and holding circuits to be used, and decides the refreshing intervals by considering the change of the voltage caused by leakage and other permissible errors of output voltage.

摘要翻译： 本发明提供了一种匹配滤波器，其可以保持与小尺寸电路相当的计算速度的整体刷新。 本发明的匹配滤波器的第一和第二加法电路分为多个组，第一和第二辅助加法器分别代替第一和第二加法器的组的功能。 然后，第一和第二加法器的输出分别输入到第一和第二减法器，并且刷新装置适当地刷新由第一和第二辅助加法器替换的组。 此外，本发明减少了要使用的辅助树苗和保持电路的数量，并且通过考虑由漏电引起的电压的变化和输出电压的其他允许误差来决定刷新间隔。

公开(公告)号：US6025752A

公开(公告)日：2000-02-15

申请号：US087924

申请日：1998-06-01

申请人： Changming Zhou ,  Guoliang Shou ,  Shengmin Lin ,  Takashi Tomatsu ,  Jie Chen

发明人： Changming Zhou ,  Guoliang Shou ,  Shengmin Lin ,  Takashi Tomatsu ,  Jie Chen

IPC分类号： H03F1/30 ,  H03F3/00 ,  H03F1/14

CPC分类号： H03F1/303 ,  H03F3/005

摘要： An inverting amplifying circuit for outputting an inversion of an input with good linearity, having an inverter circuit, a feedback capacitance, an input capacitance, a first refresh switch, a second refresh switch, a sleep switch, and a first cutoff switch. A sleep voltage is input through the sleep switch to the inverter circuit for minimizing the electrical power consumption. The sleep switch connects a terminal of the inverter circuit directly to ground when in a sleep mode. The first cut off switch is connected between an output of the inverter circuit and an output of the inverting amplifying circuit.

摘要翻译： 一种用于输出具有良好线性度的输入的反相的反相放大电路，具有反相器电路，反馈电容，输入电容，第一刷新开关，第二刷新开关，休眠开关和第一截止开关。 睡眠电压通过睡眠开关输入到逆变器电路，以最小化电力消耗。 休眠开关在休眠模式下将逆变器电路的端子直接连接到地。 第一截止开关连接在逆变器电路的输出端和反相放大电路的输出端之间。

公开(公告)号：US06388583B1

公开(公告)日：2002-05-14

申请号：US09588613

申请日：2000-06-06

申请人： Biqi Long ,  Changming Zhou

发明人： Biqi Long ,  Changming Zhou

IPC分类号： H03M700

CPC分类号： H04J13/10

摘要： The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.

摘要翻译： 本发明提供了一种方法和电路，用于产生能够在较短的等待时间内在反向信道上发送长码的代码。 该方法涉及对应于序列M或长码周期的开始之间的移位量，以及每个定时到多个掩蔽数据的组合; 确定用于响应于在尽可能快的时间点的传输请求开始生成长码的定时的掩蔽数据的组合; 以及根据掩蔽数据移动矢量的初始值。

公开(公告)号：US06625205B1

公开(公告)日：2003-09-23

申请号：US09332198

申请日：1999-06-14

申请人： Changming Zhou ,  Kunihiko Suzuki

发明人： Changming Zhou ,  Kunihiko Suzuki

IPC分类号： H04L2706

CPC分类号： H04B1/7093 ,  H04B1/708 ,  H04B2201/7071

摘要： A matched filter having a set of registers to successively store a digital voltage. The matched filter includes a cumulative shift register, a number of exclusive-or circuits, and an analog adder. The cumulative shift register has a number of stages in which each stage has one bit corresponding to the shift register. The exclusive-or circuits each perform an exclusive-or function on each bit of the digital data and the one bit coefficient while the analog adder sums outputs from the exclusive-or circuits.

摘要翻译： 具有一组寄存器以连续存储数字电压的匹配滤波器。 匹配滤波器包括累积移位寄存器，多个异或电路和模拟加法器。 累积移位寄存器具有多个阶段，其中每个级具有对应于移位寄存器的一位。 在模拟加法器对来自异或电路的输出进行求和时，异或电路各自对数字数据的每一位和一位系数进行排他或功能。

公开(公告)号：US06340942B1

公开(公告)日：2002-01-22

申请号：US09413475

申请日：1999-10-06

申请人： Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu ,  Masataka Fukui

发明人： Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu ,  Masataka Fukui

IPC分类号： H03M134

CPC分类号： H03M1/42

摘要： An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

摘要翻译： 模数转换器包括差分输入部分，其接收输入电压和参考电压，并且具有第一和第二输出端子，连接到所述第一和第二输出端子的正反馈部分，如果CMOSFET在其输入端连接到 第一输出端子，在其输入端连接到第二输出端子的第二缓冲器，以及比较电路，包括连接在第一和第二输出端子之间的第一开关部分，用于响应于比较来连接和断开第一和第二输出端子 时钟信号。 比较电路在其输出端连接到第一或第二缓冲器。 当所述切换部分响应于比较时钟信号而从连接状态变为断开状态时，比较输入电压和参考电压。

公开(公告)号：US06389438B1

公开(公告)日：2002-05-14

申请号：US09256351

申请日：1999-02-24

申请人： Changming Zhou

发明人： Changming Zhou

IPC分类号： G06J100

CPC分类号： H04B1/7093 ,  H03H17/0254 ,  H04B1/708 ,  H04B2201/7071

摘要： A matched filter and signal reception apparatus having a low power consumption and small circuitry size. In the matched filter, an analog input signal is converted to digital data by an analog to digital (A/D) converter, digital multiplication, as a correlation calculation, is executed by a plurality of exclusive-OR circuits, and an addition of outputs of the exclusive-OR circuits is performed. In the digital multiplication, the digital data is multiplied by a spreading code of one bit. The outputs from the exclusive-OR circuits are added for each weight of bits, and the addition output results are weighted and summed together.

摘要翻译： 具有低功耗和小电路尺寸的匹配滤波器和信号接收装置。 在匹配滤波器中，通过模数（A / D）转换器将模拟输入信号转换为数字数据，作为相关计算的数字乘法由多个异或电路执行，并且输出的相加 的异或电路。 在数字乘法中，数字数据乘以一位的扩展码。 对于每个比特的权重，加上来自异或电路的输出，并将加法输出结果加权并相加在一起。

公开(公告)号：US06300823B1

公开(公告)日：2001-10-09

申请号：US09257914

申请日：1999-02-26

申请人： Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu

发明人： Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu

IPC分类号： H03K500

CPC分类号： H03H15/00

摘要： A filter circuit comprises a plurality of sampling and holding circuits for sampling and holding analog input signal with a predetermined sampling period, a calculation circuit for multiplying each the analog input signal by a predetermined multiplier, and for summing the multiplication results. The sampling and holding circuits are controlled in an electrical power such that the electrical power is decreased when holding.

摘要翻译： 滤波器电路包括多个采样和保持电路，用于以预定采样周期对模拟输入信号进行采样和保持;计算电路，用于将每个模拟输入信号乘以预定乘法器，并将相乘结果相加。 采样和保持电路被控制在电力中，使得在保持时电力减小。