公开(公告)号：US06240148B1

公开(公告)日：2001-05-29

申请号：US08908919

申请日：1997-08-08

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B710

CPC classification number: H04B7/08 ,  H04B1/7115 ,  H04B2201/70701

Abstract: The present invention provides a path-diversity system featuring a small-size phase compensating circuit. This circuit calculates a compensating coefficient according to the signals of a pilot block or a pair of pilot blocks surrounding an information block, and then compensates information signals thereafter by the calculated compensating coefficient.

Abstract translation: 本发明提供一种具有小尺寸相位补偿电路的路径分集系统。 该电路根据导频块或围绕信息块的一对导频块的信号来计算补偿系数，然后通过计算的补偿系数补偿信息信号。

公开(公告)号：US6122654A

公开(公告)日：2000-09-19

申请号：US66540

申请日：1998-04-27

Applicant: Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

Inventor： Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

IPC: G06F17/10 ,  G06F17/16 ,  G06G7/22 ,  H03F1/34 ,  H03H15/00 ,  H03H17/02 ,  G06F7/52

CPC classification number: G06G7/22

Abstract: A complex multiplication circuit of a calculation formula equivalent but different from the usual formula.The calculation formula is as follows:Pr={x(a+b)-b(x+y)} equivalent to (ax-by)Pi={y(a-b)+b(x+y)} equivalent to (ay+bx)Here,Input signal: x+jyMultiplier:a+jbMultiplication result:Pr+jPi.

Abstract translation: 计算公式的复乘法电路等效但不同于通常的公式。 计算公式如下：等价于（ay）的（ax-by）Pi = {y（ab）+ b（x + y）}的Pr = {x（a + b）-b（x + y） + bx）这里，输入信号：x + jy乘数：a + jb乘法结果：Pr + jPi。

公开(公告)号：US6073149A

公开(公告)日：2000-06-06

申请号：US60000

申请日：1998-04-15

Applicant: Guoliang Shou ,  Kazunori Motohashi ,  Ying Chen ,  Takashi Tomatsu ,  Changming Zhou ,  Jie Chen

Inventor： Guoliang Shou ,  Kazunori Motohashi ,  Ying Chen ,  Takashi Tomatsu ,  Changming Zhou ,  Jie Chen

IPC: G06F7/49 ,  G06J1/00 ,  G06F7/00 ,  G06G7/00

CPC classification number: G06F7/49 ,  G06F2207/386

Abstract: A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.

Abstract translation: 一种用于多值附加的计算电路，包括并行加法器，输出加法器，量化部分和逻辑转换部分。 上述量化部分中的上述加法器和阈值电路中的加法电路由包括电容耦合的电压驱动电路组成。

公开(公告)号：US5974038A

公开(公告)日：1999-10-26

申请号：US864784

申请日：1997-05-29

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H04B1/707 ,  H04B1/7075 ,  H04B1/7093 ,  H04B1/7115 ,  H04L7/00 ,  H04B7/216

CPC classification number: H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

Abstract: This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.

Abstract translation: 本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。 接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。 该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。 当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号 。 此外，进行解扩。 来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

公开(公告)号：US5930290A

公开(公告)日：1999-07-27

申请号：US841217

申请日：1997-04-30

Applicant: Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

Inventor： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

IPC: H04B1/707 ,  H04B1/7093 ,  H04J13/10 ,  H04B15/00 ,  H04B7/216

CPC classification number: H04J13/0077 ,  H04B1/7093

Abstract: A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.

Abstract translation: 提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。 要发送的一系列数字数据被分为4位帧。 每帧的4位数据按预定顺序分成第一至第四元素。 第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。 要传输的数据的频谱通过乘以这些复数来传播。 四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。 根据匹配滤波器的输出，恢复第一至第四元件。

公开(公告)号：US5872466A

公开(公告)日：1999-02-16

申请号：US686950

申请日：1996-07-26

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H03H11/04 ,  H03H17/02 ,  H04B1/707 ,  H04B1/7093 ,  H04L7/00 ,  H04L7/10 ,  H03K5/00

CPC classification number: H03H11/04 ,  H03H17/0254

Abstract: A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

Abstract translation: 公开了具有降低的电力消耗的匹配滤波器。 由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。 由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。 各组中的信号通过电容耦合并联并且在电路中间歇地供电。

公开(公告)号：US5783961A

公开(公告)日：1998-07-21

申请号：US764637

申请日：1996-12-11

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H03K19/0948 ,  H03F1/02 ,  H03F1/34 ,  H03F3/46 ,  H03F3/72 ,  H03K5/153 ,  H03H11/26

CPC classification number: H03F3/72

Abstract: The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

Abstract translation: 本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。 在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。 当反相放大电路不工作时，MOS开关打开。

公开(公告)号：US6081549A

公开(公告)日：2000-06-27

申请号：US4607

申请日：1998-01-08

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

IPC: H04B1/707 ,  H04B1/712 ,  H04B7/01 ,  H04B7/08 ,  H04K1/00

CPC classification number: H04B1/711 ,  H04B7/01 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70701

Abstract: Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31-34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31-34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction A circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error. In this way, the correction vectors are sequentially modified based on the temporary determination results for the information symbols.

Abstract translation: 通过最小的电路以高精度校正扩频信号的相位。 接收机的相位校正电路31-34中的一个对应于每个路径。 解扩输出的I分量和Q分量被提供给相位校正电路31-34。 相位误差提取器1从接收到的导频块中提取第一相位误差。 相位校正器2使用已经基于第一相位误差计算的校正矢量校正接收信息符号的相位误差。 RAKE合成器25将校正的接收信号与其他路径的相位校正A电路的输出合成，并将合成信号输出到暂时确定要处理的信息符号的临时确定器3。 使用临时确定结果在校正矢量修改器4中修改相位误差。 基于修正的相位误差计算新的校正矢量。 以这种方式，基于信息符号的临时确定结果，顺序修改校正矢量。

公开(公告)号：US06064690A

公开(公告)日：2000-05-16

申请号：US75861

申请日：1998-05-12

Applicant: Changming Zhou ,  Xuping Zhou ,  Guolinag Shou

Inventor： Changming Zhou ,  Xuping Zhou ,  Guolinag Shou

IPC: H04B1/707 ,  H04B1/69

CPC classification number: H04B1/707 ,  H04B1/7093

Abstract: A spread spectrum communication system wherein spreading codes for in-phase and quadrature components are composed by addition and subtraction and the received signal is multiplied by these composed codes for despreading. The communication system comprises a transmitter generating in-phase and quadrature components. The transmitter includes a spreading circuit for spreading the in-phase and quadrature components. The system further includes a receiver, a phase correction circuit for correcting the phase of despreaded components, a rake combiner for combining the components corrected by the phase correction circuit and a circuit for outputting a combined signal and a delay detection circuit for delaying detection of the combined signal. The receiver also comprises a provisional judgment portion for judging the phase of a pair of the in-phase and quadrature phase components. The phase correction circuit corrects the phase according to the phase judged by the provisional judgment portion.

Abstract translation: 扩展频谱通信系统，其中用于同相和正交分量的扩展码由加法和减法组成，并且接收的信号乘以这些组合代码用于解扩。 通信系统包括产生同相和正交分量的发射机。 发射机包括用于扩展同相和正交分量的扩展电路。 该系统还包括接收机，用于校正解扩部件的相位的相位校正电路，用于组合由相位校正电路校正的分量的组合器和用于输出组合信号的电路和延迟检测电路的延迟检测电路 组合信号。 接收机还包括用于判断一对同相和正交相位分量的相位的临时判断部分。 相位校正电路根据由临时判断部判定的相位来校正相位。

公开(公告)号：US5958002A

公开(公告)日：1999-09-28

申请号：US905784

申请日：1997-08-12

Applicant: Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC: G06G7/25 ,  G06G7/22 ,  G06G7/00 ,  G06G7/16

CPC classification number: G06G7/22

Abstract: A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##

Abstract translation: 高精度矢量绝对值计算电路采用模拟处理和最小硬件。 对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及 它们都被转换为绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值 通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。 从输出端子27输出由下式计算的复数绝对值。