公开(公告)号：US11650953B2

公开(公告)日：2023-05-16

申请号：US17072918

申请日：2020-10-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Kirk M. Bresniker ,  Paolo Faraboschi ,  John Paul Strachan

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/7867 ,  G06F9/30145 ,  G06F9/3897

Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.

公开(公告)号：US11018692B2

公开(公告)日：2021-05-25

申请号：US16942293

申请日：2020-07-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Anirban Nag ,  Naveen Muralimanohar ,  Paolo Faraboschi

IPC: H03M7/30 ,  H03M7/24

Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

公开(公告)号：US20200341898A1

公开(公告)日：2020-10-29

申请号：US16925870

申请日：2020-07-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Alexandros Daglis ,  Paolo Faraboschi ,  Qiong Cai ,  Gary Gostin

IPC: G06F12/0817 ,  G06F12/14 ,  G06F12/0831

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

公开(公告)号：US10698878B2

公开(公告)日：2020-06-30

申请号：US15556238

申请日：2015-03-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Stanko Novakovic ,  Kimberly Keeton ,  Paolo Faraboschi ,  Robert Schreiber

IPC: G06F16/23 ,  G06F16/901 ,  G06F16/27

Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.

公开(公告)号：US10592431B2

公开(公告)日：2020-03-17

申请号：US16101997

申请日：2018-08-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Marshall Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F12/109 ,  G06F12/1009

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

公开(公告)号：US10579519B2

公开(公告)日：2020-03-03

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US20200050553A1

公开(公告)日：2020-02-13

申请号：US16101997

申请日：2018-08-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Marshall Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F12/109 ,  G06F12/1009

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

公开(公告)号：US10452472B1

公开(公告)日：2019-10-22

申请号：US15997030

申请日：2018-06-04

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  John Paul Strachan ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09 ,  H03M13/35

Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.

公开(公告)号：US10303622B2

公开(公告)日：2019-05-28

申请号：US15500460

申请日：2015-03-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Naveen Muralimanohar ,  Gregg B. Lesartre ,  Paolo Faraboschi ,  Jishen Zhao

IPC: G06F21/00 ,  G06F12/14 ,  H03M7/30 ,  G06F3/06 ,  G06F11/10 ,  H03M13/09

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

公开(公告)号：US20190065408A1

公开(公告)日：2019-02-28

申请号：US15693149

申请日：2017-08-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S Milojicic ,  Chris I Dalton ,  Paolo Faraboschi ,  Kirk M. Bresniker

IPC: G06F12/14

Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.