公开(公告)号：US20050215222A1

公开(公告)日：2005-09-29

申请号：US11121018

申请日：2005-05-04

申请人： Taizo Yamawaki ,  Takefumi Endo ,  Kazuo Watanabe ,  Kazuaki Hori ,  Julian Hildersley

发明人： Taizo Yamawaki ,  Takefumi Endo ,  Kazuo Watanabe ,  Kazuaki Hori ,  Julian Hildersley

IPC分类号： H03L7/10 ,  H03D13/00 ,  H03L7/00 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/16 ,  H03L7/18 ,  H04B1/3822 ,  H04B1/40 ,  H04L7/033

CPC分类号： H03L7/10 ,  H03D13/007 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/406

摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

公开(公告)号：US06424787B1

公开(公告)日：2002-07-23

申请号：US09774662

申请日：2001-02-01

申请人： Katsuyuki Watanabe ,  Hideo Nishijima ,  Koichi Ono ,  Akihito Nishizawa ,  Kazuaki Hori

发明人： Katsuyuki Watanabe ,  Hideo Nishijima ,  Koichi Ono ,  Akihito Nishizawa ,  Kazuaki Hori

IPC分类号： H04N576

摘要： A magnetic recording/reproducing apparatus equipped with an image sensor, has a camera portion having an A/D converter for converting a signal from an image sensor into a digital signal and a first digital processor for receiving an output of the A/D converter and for digitally processing thereof. A VTR portion of a helical scan type mounts at least two or more of magnetic heads for recording/reproducing a FM modulated luminance signal and a low band converted chrominance signal. A second digital processor processes a video signal of the VTR. A switching circuit is provided in a preceding stage of the A/D converter. The image sensor signal, an external video signal and a reproduced signal from the magnetic heads are exchanged. The output of the A/D converter is inputed to the second digital processor, and a sampling clock of the A/D converter is exchanged to the most appropriate clock for the respective image sensor signal, the external video signal and the reproduced signal from the magnetic heads.