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公开(公告)号：US07333779B2
公开(公告)日：2008-02-19
申请号：US11121018
申请日：2005-05-04
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
摘要翻译： 在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。 在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。 可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。 相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。
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公开(公告)号：US20050215222A1
公开(公告)日：2005-09-29
申请号：US11121018
申请日：2005-05-04
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
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公开(公告)号：US06970683B2
公开(公告)日：2005-11-29
申请号：US10375241
申请日：2003-02-28
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
摘要翻译： 在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。 在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。 可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。 相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。
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公开(公告)号：US06996377B1
公开(公告)日：2006-02-07
申请号：US09787380
申请日：1999-09-14
IPC分类号： H04B1/40
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
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公开(公告)号：US07224948B1
公开(公告)日：2007-05-29
申请号：US10148960
申请日：2000-01-11
申请人： Taizo Yamawaki , Satoshi Tanaka , Masaru Kokubo , Kazuo Watanabe , Masumi Kasahara , Kazuaki Hori , Julian Hildersley
发明人： Taizo Yamawaki , Satoshi Tanaka , Masaru Kokubo , Kazuo Watanabe , Masumi Kasahara , Kazuaki Hori , Julian Hildersley
CPC分类号： H03C3/0983 , H03C3/0925 , H03C3/0966 , H03D7/163 , H03J2200/17 , H03L7/23 , H04B1/0475 , H04B2001/0491 , H04L25/03343
摘要： There are provided a transmitter and a wireless communication terminal apparatus using the same for solving a problem of undesired spurs due to harmonics of an output signal of a frequency synthesizer, and further solving a problem of the undesired spurs occurring when the harmonics of an output signal of a crystal oscillator are mixed into a VCO to facilitate to design a circuit or a mounting substrate. The transmitter has a relationship between an output frequency of a PLL frequency conversion circuit (5) and output frequencies of frequency synthesizers (1, 2) stored therein, and the output frequencies of the frequency synthesizers (1, 2) input into the PLL frequency conversion circuit (5) are controlled on the basis of the relationship so that the undesired spurs are suppressed. Thereby, even when the undesired spurs occur in the output of the transmitter due to a crosstalk between circuits or through a substrate, which can be easily suppressed, it is therefore possible to reduce time and cost for redesigning the circuit or the substrate.
摘要翻译： 提供了一种使用该发送器和无线通信终端装置的方法，用于解决由于频率合成器的输出信号的谐波引起的不期望的杂散问题，并且进一步解决了当输出信号的谐波发生时出现的不需要的杂散的问题 的晶体振荡器混合到VCO中以便于设计电路或安装衬底。 发射机具有PLL频率转换电路（5）的输出频率和存储在其中的频率合成器（1,2）的输出频率与输入到PLL频率的频率合成器（1,2）的输出频率之间的关系 基于该关系来控制转换电路（5），从而抑制不需要的杂散。 因此，即使由于电路之间的串扰或通过可以容易地抑制的基板而在发射机的输出端发生不想要的杂散，因此可以减少重新设计电路或基板的时间和成本。
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公开(公告)号：US06639933B2
公开(公告)日：2003-10-28
申请号：US09993764
申请日：2001-11-27
IPC分类号： H03D324
摘要： A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency, and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal, a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter, the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.
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7.发明授权
公开(公告)号：US6163585A
公开(公告)日：2000-12-19
申请号：US16302
申请日：1998-01-30
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40 , H04L7/00 , H04L5/16
摘要： A phase-locked loop circuit includes a current output type phase comparator for converting a phase difference between a first signal and a second signal into a current signal to be outputted, a low pass filter for filtering the current signal of the current output type phase comparator to produce an output signal, a voltage controlled oscillator for producing an output signal having a frequency corresponding to the output signal of the low pass filter, a current source for supplying a current to an input of the low pass filter, a reset switch for applying to the voltage controlled oscillator a reset voltage for canceling a phase-locked state of the phase-locked loop, and a frequency converter for frequency-converting the output signal of the voltage controlled oscillator to produce the second signal.
摘要翻译： 锁相环电路包括电流输出型相位比较器，用于将第一信号和第二信号之间的相位差转换为要输出的电流信号;低通滤波器，用于对电流输出型相位比较器 产生输出信号的压控振荡器，用于产生具有与低通滤波器的输出信号对应的频率的输出信号的压控振荡器，用于向低通滤波器的输入端提供电流的电流源， 向压控振荡器施加用于消除锁相环的锁相状态的复位电压;以及频率变换器，用于对压控振荡器的输出信号进行频率转换以产生第二信号。
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8.发明授权公开(公告)号：US07266171B2
公开(公告)日：2007-09-04
申请号：US10641136
申请日：2003-08-15
摘要： A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.
摘要翻译： 通信装置包括锁相环电路，其接收具有频率的第一信号并将其转换为具有发送频率的输出信号，并且包括电流输出型相位比较器，其转换第一信号和第二信号之间的相位差 将低通滤波器滤波电流输出型相位比较器的电流信号以产生输出信号，该压控振荡器产生具有与低通滤波器的输出信号对应的发送频率的输出信号， 构成锁相环电路的输出信号的压控振荡器的输出信号，对压控振荡器的输出信号进行频率转换以产生第二信号的频率转换器，以及向 输入低通滤波器。
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9.发明授权公开(公告)号：US06324219B2
公开(公告)日：2001-11-27
申请号：US09729721
申请日：2000-12-06
IPC分类号： H04L2704
摘要： A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts the first signal into an output signal having a transmission frequency. The phase-locked loop circuit includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal, a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter, the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, and a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal.
摘要翻译： 通信装置包括锁相环电路，其接收具有频率的第一信号，并将第一信号转换为具有发送频率的输出信号。 锁相环电路包括电流输出型相位比较器，其将第一信号和第二信号之间的相位差转换为电流信号;低通滤波器，其对当前输出型相位比较器的电流信号进行滤波， 输出信号，产生具有与低通滤波器的输出信号对应的发送频率的输出信号的压控振荡器，构成锁相环电路的输出信号的压控振荡器的输出信号，以及频率 转换器，其对压控振荡器的输出信号进行频率转换以产生第二信号。
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公开(公告)号：US08093946B2
公开(公告)日：2012-01-10
申请号：US12558090
申请日：2009-09-11
申请人： Gerard Wimpenny , Julian Hildersley , Robert Henshaw , Yi Qin
发明人： Gerard Wimpenny , Julian Hildersley , Robert Henshaw , Yi Qin
IPC分类号： H03G3/20
CPC分类号： H03F1/32 , H03F1/0227 , H03F1/0266 , H03F2200/102 , H03F2200/228 , H03F2200/504
摘要： There is disclosed a technique for controlling at least one amplification stage, comprising: selecting a linearity objective for the amplification stage; in dependence on an input signal to said amplification stage, determining a combination of supply input and bias input for the amplification stage in order to meet said linearity objective; and in dependence on there being more than one combination of supply input and bias input for meeting the linearity objective, selecting the combination that optimizes a further system performance objective for the amplification stage. The further system performance objective may be one or more of: an efficiency objective; an envelope signal bandwidth objective; or a robustness to production tolerance objective.
摘要翻译： 公开了一种用于控制至少一个放大级的技术，包括：选择放大级的线性度; 根据对所述放大级的输入信号，确定用于放大级的电源输入和偏置输入的组合，以便满足所述线性目标; 并且依赖于用于满足线性度目标的供给输入和偏置输入的多于一个组合，选择优化用于放大级的另一系统性能目标的组合。 进一步的系统性能目标可以是一个或多个：效率目标; 包络信号带宽目标; 或对生产容忍目标的鲁棒性。
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