公开(公告)号：US20080298156A1

公开(公告)日：2008-12-04

申请号：US12170055

申请日：2008-07-09

申请人： Kenji YOSHINAGA ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

发明人： Kenji YOSHINAGA ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G11C29/48 ,  G11C29/12 ,  G11C29/12005

摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

摘要翻译： 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。

公开(公告)号：US20060132247A1

公开(公告)日：2006-06-22

申请号：US11311301

申请日：2005-12-20

申请人： Masanobu Kishida ,  Fukashi Morishita

发明人： Masanobu Kishida ,  Fukashi Morishita

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  H03K17/063

摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

摘要翻译： 本发明提供一种即使在以低电源电压驱动的情况下也能够稳定工作的电流限制型振荡器和使用该振荡器的电荷泵电路。 限流振荡器具有延迟部分，该延迟部分包括多个串联的反相器，用于基于限流电平指示信号来延迟输出脉冲，并且该振荡器还包括至少一个第一晶体管，其限制第一电流 所述逆变器和高电位电源以及限制所述逆变器之间的第二电流和低电位电源的至少一个第二晶体管，其中所述多个逆变器中的至少一个被配置为与所述第一逆变器连接的第一逆变器 并且不与第二晶体管连接，并且多个反相器中的至少另一个被配置为不与第一晶体管连接并与第二晶体管连接的第二反相器。

公开(公告)号：US20050264347A1

公开(公告)日：2005-12-01

申请号：US11135488

申请日：2005-05-24

申请人： Takayuki Gyohten ,  Fukashi Morishita

发明人： Takayuki Gyohten ,  Fukashi Morishita

IPC分类号： H01L27/04 ,  G05F1/10 ,  G05F1/46 ,  G05F3/24 ,  G11C11/407 ,  H01L21/822

CPC分类号： G05F1/465

摘要： A voltage for reference at a voltage level higher than a target value is produced from a constant current provided from a constant current generating circuit, and is subjected to resistance division by a resistance division circuit to produce a reference voltage at the target level, and then a final reference voltage is produced by a voltage follower. An internal voltage generating circuit thus provided can generate the reference voltage having the desired voltage level with high accuracy as well as an internal voltage based on the reference voltage by controlling temperature characteristic even with a low power supply voltage.

摘要翻译： 在从恒定电流产生电路提供的恒定电流中产生高于目标值的电压电压的参考电压，并通过电阻分割电路进行电阻分割以产生目标电平的参考电压，然后 最终的参考电压由电压跟随器产生。 由此提供的内部电压产生电路即使在低电源电压下也可以通过控制温度特性，以高精度产生具有所需电压电平的基准电压以及基于参考电压的内部电压。

公开(公告)号：US06819619B2

公开(公告)日：2004-11-16

申请号：US10356560

申请日：2003-02-03

申请人： Fukashi Morishita ,  Hiroshi Kato

发明人： Fukashi Morishita ,  Hiroshi Kato

IPC分类号： G11C514

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C5/147 ,  G11C2207/104

摘要： A semiconductor memory device includes a memory cell array, a data bus, a reference voltage generating circuit, a voltage down converter, a VPP generating circuit, a circuit group, and a test circuit. The reference voltage generating circuit, voltage down converter, and VPP generating circuit include thick film transistors having a gate oxide film thickness suitable to a power supply voltage of 3.3 V. Circuits included in the circuit group include thin film transistors having a gate oxide film thickness suitable to a power supply voltage of 1.5 V. The reference voltage generating circuit, voltage down converter, and VPP generating circuit including the thick film transistors are arranged to form units corresponding to the position of the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，数据总线，参考电压产生电路，降压转换器，VPP生成电路，电路组和测试电路。 参考电压产生电路，降压转换器和VPP产生电路包括具有适合于3.3V的电源电压的栅极氧化膜厚度的厚膜晶体管。电路组中包括的电路包括具有栅氧化物膜厚度 适合于1.5V的电源电压。包括厚膜晶体管的参考电压产生电路，降压转换器和VPP产生电路被布置成形成与存储单元阵列的位置对应的单元。

公开(公告)号：US06434078B1

公开(公告)日：2002-08-13

申请号：US09503719

申请日：2000-02-14

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G11C514

CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C29/12

摘要： In a voltage down converter, an internal power supply potential can be made equal to an external power supply potential by rendering an output driving transistor included in differential amplifiers conductive in accordance with an activation of a burn-in mode detection signal. The differential amplifiers include a comparison circuit having an output changed to an inactive state in response to the burn-in mode detection signal and a transistor setting a level of a gate voltage of the drive transistor to a fixed level.

公开(公告)号：US06424134B1

公开(公告)日：2002-07-23

申请号：US09759321

申请日：2001-01-16

申请人： Fukashi Morishita ,  Akira Yamazaki ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Kobayashi

发明人： Fukashi Morishita ,  Akira Yamazaki ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Kobayashi

IPC分类号： G05F316

摘要： A semiconductor device includes a constant voltage generation circuit generating a constant voltage commonly to reference voltages corresponding to a plurality of internal voltages. The plurality of reference voltages are generated from the common constant voltage. Thus, the semiconductor device for generating internal voltages is implemented, which allows reduction in layout area and decrease in test time for voltage adjustment.

公开(公告)号：US06392472B1

公开(公告)日：2002-05-21

申请号：US09954218

申请日：2001-09-18

申请人： Mako Kobayashi ,  Fukashi Morishita

发明人： Mako Kobayashi ,  Fukashi Morishita

IPC分类号： G05F1575

CPC分类号： G05F1/465

摘要： A voltage generation circuit includes a digital type VDC. The digital VDC includes a differential amplify circuit amplifying a voltage deviation of a reference voltage signal from a detection voltage signal to output the amplified voltage to a control node, a signal conversion circuit providing either an H level or an L level according to the voltage level of the control node, and an output transistor connecting an external power supply line and an internal power supply voltage node according to an output voltage of the signal conversion circuit. The center of the range of the varying voltage level of the control node is set by shifting to the logic threshold value of the signal conversion circuit.

摘要翻译： 电压产生电路包括数字型VDC。 数字VDC包括差分放大电路，放大参考电压信号与检测电压信号的电压偏差，以将放大的电压输出到控制节点，信号转换电路根据电压电平提供H电平或L电平 以及根据所述信号转换电路的输出电压连接外部电源线和内部电源电压节点的输出晶体管。 通过转移到信号转换电路的逻辑阈值来设定控制节点的变化电压电平的范围的中心。

公开(公告)号：US06385117B1

公开(公告)日：2002-05-07

申请号：US09843691

申请日：2001-04-30

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G11C800

摘要： A voltage generating circuit of the present invention includes a charge pump regulator and a voltage converting circuit. Charge pump regulator receives Ext.Vcc and a ground voltage as inputs and outputs a negative voltage Vbb1. Charge pump regulator receives Int.Vcc and negative voltage Vbb1 as inputs and outputs negative voltage Vbb2(

公开(公告)号：US06323689B1

公开(公告)日：2001-11-27

申请号：US09088703

申请日：1998-06-02

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： H01L2500

CPC分类号： H01L27/0251

摘要： The interlayer capacitance between a first metal interconnection through which a control signal is transmitted to the gate of a drive transistor and respective power supply interconnections through which a power supply potential and a ground potential is supplied is sufficiently smaller than the interlayer capacitance between an interconnection connecting a drain of the drive transistor and the first metal interconnection. The power supply interconnection is not coupled to a signal input to the gate of the drive transistor.

摘要翻译： 通过其将控制信号传输到驱动晶体管的栅极的第一金属互连和供电电位和接地电位之间的相互供电互连的层间电容充分小于互连连接 驱动晶体管的漏极和第一金属互连。 电源互连不耦合到输入到驱动晶体管的栅极的信号。

公开(公告)号：US5877978A

公开(公告)日：1999-03-02

申请号：US710215

申请日：1996-09-13

申请人： Fukashi Morishita ,  Shigeki Tomishima ,  Kazutani Arimoto

发明人： Fukashi Morishita ,  Shigeki Tomishima ,  Kazutani Arimoto

IPC分类号： H01L21/76 ,  G11C11/401 ,  G11C11/404 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C11/4074 ,  H01L29/7841

摘要： In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.